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Travelled to:
1 × France
1 × USA
Collaborated with:
M.Corbalan A.Keval D.Lisk R.Radojcic M.Nowak A.S.Arani X.Hu H.Peng C.Cheng W.Yu M.Popovich X.Chen
Talks about:
challeng (1) silicon (1) reliabl (1) system (1) signal (1) integr (1) stack (1) power (1) plan (1) awar (1)

Person: Thomas Toms

DBLP DBLP: Toms:Thomas

Contributed to:

DAC 20132013
DATE 20092009

Wrote 2 papers:

DAC-2013-CorbalanKTLRN #3d #challenge
Power and signal integrity challenges in 3D systems (MC, AK, TT, DL, RR, MN), p. 4.
DATE-2009-AraniHPCYPTC #3d #reliability
Reliability aware through silicon via planning for 3D stacked ICs (ASA, XH, HP, CKC, WY, MP, TT, XC), pp. 288–291.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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