Travelled to:2 × France
2 × Germany
3 × USA
Collaborated with:H.Zhuang C.Cheng W.Zhang K.Zhai C.Hu H.Peng L.Zhang I.Kang X.Wang Y.Xu Q.Chen L.Jiang N.Wong Z.Wang Z.Yu R.Jiang J.Xiong A.S.Arani X.Hu M.Popovich T.Toms X.Chen H.Zhu A.Deutsch G.A.Katopis D.M.Dreps E.S.Kuh W.Zhang Y.Zhu R.Shi Z.Zhu L.Chua-Eoan R.Murgai T.Shibuya N.Ito
Talks about:extract (3) capacit (3) variat (3) effici (3) interconnect (2) algorithm (2) power (2) chip (2) awar (2) use (2)
Person: Wenjian Yu
DBLP: Yu:Wenjian
Contributed to:
2015
201320122009200920082008Wrote 8 papers:
- DAC-2015-ZhuangYKWC #algorithm #exponential #framework #performance #scalability #simulation #using
- An algorithmic framework for efficient large-scale circuit simulation using exponential integrators (HZ, WY, IK, XW, CKC), p. 6.
- DATE-2013-ZhaiYZ #algorithm #float #random
- GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects (KZ, WY, HZ), pp. 1661–1666.
- DATE-2012-XuYCJW #3d #performance
- Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC (YX, WY, QC, LJ, NW), pp. 1409–1412.
- DAC-2009-YuHZ
- Variational capacitance extraction of on-chip interconnects based on continuous surface model (WY, CH, WZ), pp. 758–763.
- DATE-2009-AraniHPCYPTC #3d #reliability
- Reliability aware through silicon via planning for 3D stacked ICs (ASA, XH, HP, CKC, WY, MP, TT, XC), pp. 288–291.
- DAC-2008-ZhangYZDKDKC #optimisation #power management #using
- Low power passive equalizer optimization using tritonic step response (LZ, WY, HZ, AD, GAK, DMD, ESK, CKC), pp. 570–573.
- DATE-2008-ZhangYWYJX #correlation #performance #process #statistics
- An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation (WZ, WY, ZW, ZY, RJ, JX), pp. 580–585.
- DATE-2008-ZhangZYZSPZCMSIC #multi #network
- Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (WZ, YZ, WY, LZ, RS, HP, ZZ, LCE, RM, TS, NI, CKC), pp. 537–540.