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Travelled to:
1 × France
1 × Germany
Collaborated with:
C.Cheng W.Yu A.S.Arani X.Hu M.Popovich T.Toms X.Chen W.Zhang Y.Zhu L.Zhang R.Shi Z.Zhu L.Chua-Eoan R.Murgai T.Shibuya N.Ito
Talks about:
transistor (1) parallel (1) silicon (1) reliabl (1) network (1) circuit (1) voltag (1) violat (1) domain (1) worst (1)

Person: He Peng


Contributed to:

DATE 20092009
DATE 20082008

Wrote 3 papers:

DATE-2009-AraniHPCYPTC #3d #reliability
Reliability aware through silicon via planning for 3D stacked ICs (ASA, XH, HP, CKC, WY, MP, TT, XC), pp. 288–291.
DATE-2009-PengC #parallel #simulation
Parallel transistor level full-chip circuit simulation (HP, CKC), pp. 304–307.
DATE-2008-ZhangZYZSPZCMSIC #multi #network
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (WZ, YZ, WY, LZ, RS, HP, ZZ, LCE, RM, TS, NI, CKC), pp. 537–540.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.