Travelled to:1 × France
5 × USA
Collaborated with:S.M.Nowick G.Venkataramani S.C.Goldstein M.Budiu A.Bardsley D.A.Edwards M.Mishra T.J.Callahan
Talks about:system (4) asynchron (2) spatial (2) comput (2) time (2) resynthesi (1) transform (1) synthesi (1) protocol (1) interfac (1)
Person: Tiberiu Chelcea
DBLP: Chelcea:Tiberiu
Contributed to:
2007
200620042002
20022001Wrote 7 papers:
- DAC-2007-ChelceaVG #self
- Self-Resetting Latches for Asynchronous Micro-Pipelines (TC, GV, SCG), pp. 986–989.
- DAC-2007-VenkataramaniBCG #analysis
- Global Critical Path: A Tool for System-Level Timing Analysis (GV, MB, TC, SCG), pp. 783–786.
- ASPLOS-2006-MishraCCVGB #execution #named
- Tartan: evaluating spatial computation for whole program execution (MM, TJC, TC, GV, SCG, MB), pp. 163–174.
- ASPLOS-2004-BudiuVCG
- Spatial computation (MB, GV, TC, SCG), pp. 14–26.
- DAC-2002-ChelceaN #optimisation #scalability
- Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems (TC, SMN), pp. 405–410.
- DATE-2002-ChelceaNBE #synthesis
- A Burst-Mode Oriented Back-End for the Balsa Synthesis System (TC, SMN, AB, DAE), pp. 330–337.
- DAC-2001-ChelceaN #interface #protocol #robust
- Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols (TC, SMN), pp. 21–26.