BibSLEIGH corpus
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Travelled to:
3 × USA
Collaborated with:
L.Soulé K.Choi S.Y.Hwang M.Stefik W.M.v.Cleemput S.Junuzovic K.Inkpen A.Gupta
Talks about:
algorithm (2) parallel (2) simul (2) share (2) architectur (1) processor (1) increment (1) general (1) surfac (1) purpos (1)

Person: Tom Blank

DBLP DBLP: Blank:Tom

Contributed to:

CHI 20122012
DAC 19881988
DAC 19811981

Wrote 4 papers:

CHI-2012-JunuzovicIBG #named
IllumiShare: sharing any surface (SJ, KI, TB, AG), pp. 1919–1928.
DAC-1988-ChoiHB #algorithm #simulation
Incremental-in-time Algorithm for Digital Simulation (KC, SYH, TB), pp. 501–505.
DAC-1988-SouleB #logic #parallel #simulation
Parallel Logic Simulation on General Purpose Machines (LS, TB), pp. 166–171.
DAC-1981-BlankSC #algorithm #architecture #parallel
A parallel bit map processor architecture for DA algorithms (TB, MS, WMvC), pp. 837–845.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.