Travelled to:1 × France
2 × Germany
2 × USA
Collaborated with:G.G.E.Gielen T.McConaghy W.M.C.Sansen R.Schoofs M.Steyaert W.Daems
Talks about:hierarch (4) analog (4) synthesi (3) perform (3) circuit (3) model (3) methodolog (2) integr (2) effici (2) optim (2)
Person: Tom Eeckelaert
DBLP: Eeckelaert:Tom
Contributed to:
2007
2006200520052003Wrote 6 papers:
- DATE-2007-EeckelaertSGSS #performance #synthesis
- An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection (TE, RS, GGEG, MS, WMCS), pp. 81–86.
- DAC-2006-EeckelaertSGSS #design #optimisation #standard
- Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard (TE, RS, GGEG, MS, WMCS), pp. 25–30.
- DAC-2005-GielenME #modelling #performance #synthesis
- Performance space modeling for hierarchical synthesis of analog integrated circuits (GGEG, TM, TE), pp. 881–886.
- DATE-2005-EeckelaertMG #multi #performance #synthesis #using
- Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces (TE, TM, GGEG), pp. 1070–1075.
- DATE-2005-McConaghyEG #canonical #generative #named #programming #search-based
- CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming (TM, TE, GGEG), pp. 1082–1087.
- DATE-2003-EeckelaertDGS #modelling #performance
- Generalized Posynomial Performance Modeling (TE, WD, GGEG, WMCS), pp. 10250–10255.