Travelled to:1 × France
1 × Germany
1 × USA
Collaborated with:M.J.Garzarán D.S.Gracia J.L.Briz P.E.Ibáñez M.Ortín M.Villarroya C.Izu T.Monreal F.Vallejo R.Beivide M.Prvulovic J.M.Llabería L.Rauchwerger J.Torrellas
Talks about:multiprocessor (2) hardwar (2) construct (1) character (1) tradeoff (1) prefetch (1) traffic (1) reactiv (1) pattern (1) homogen (1)
Person: Víctor Viñals
DBLP: Vi=ntilde=als:V=iacute=ctor
Contributed to:
20142009
2003
2001Wrote 4 papers:
- DATE-2014-OrtinGVIV
- Dynamic construction of circuits for reactive traffic in homogeneous CMPs (MO, DSG, MV, CI, VV), pp. 1–4.
- DATE-2009-GraciaMVBV #latency
- Light NUCA: A proposal for bridging the inter-cache latency gap (DSG, TM, FV, RB, VV), pp. 530–535.
- HPCA-2003-GarzaranPLVRT #concurrent #memory management #multi #thread #trade-off
- Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors (MJG, MP, JML, VV, LR, JT), pp. 191–202.
- PDP-2001-GarzaranBIV #effectiveness #hardware #multi
- Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware (MJG, JLB, PEI, VV), pp. 345–354.