Travelled to:1 × USA
Collaborated with:J.Chhugani A.D.Nguyen P.Dubey C.Kim N.Satish Yuxin Bai E.Ipek E.Sedlar T.Kaldewey D.Kim S.A.Brandt A.D.Blas W.Macy M.Hagog Y.Chen A.Baransi S.Kumar
Talks about:sort (4) fast (4) cpus (3) architectur (2) implement (2) modern (2) effici (2) multi (2) simd (2) gpus (2)
Person: Victor W. Lee
DBLP: Lee:Victor_W=
Contributed to:
2010
20092008
2017Wrote 5 papers:
- SIGMOD-2010-KimCSSNKLBD #architecture #named #performance
- FAST: fast architecture sensitive tree search on modern CPUs and GPUs (CK, JC, NS, ES, ADN, TK, VWL, SAB, PD), pp. 339–350.
- SIGMOD-2010-SatishKCNLKD #performance
- Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort (NS, CK, JC, ADN, VWL, DK, PD), pp. 351–362.
- VLDB-2009-KimSCKNBLSD #implementation #manycore #performance
- Sort vs. Hash Revisited: Fast Join Implementation on Modern Multi-Core CPUs (CK, ES, JC, TK, ADN, ADB, VWL, NS, PD), pp. 1378–1389.
- VLDB-2008-ChhuganiNLMHCBKD #architecture #cpu #implementation #manycore #performance #sorting
- Efficient implementation of sorting on multi-core SIMD CPU architecture (JC, ADN, VWL, WM, MH, YKC, AB, SK, PD), pp. 1313–1324.
- ASPLOS-2017-BaiLI #performance #power management
- Voltage Regulator Efficiency Aware Power Management (YB, VWL, EI), pp. 825–838.