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Travelled to:
1 × France
2 × Germany
3 × USA
Collaborated with:
K.Chakrabarty E.J.Marinissen C.Liu G.Grise M.Taylor A.Sehgal M.D.Krasniewski A.Chandra S.Schweizer
Talks about:
test (6) optim (4) tam (4) soc (4) use (3) wrapper (2) schedul (2) reduct (2) data (2) chip (2)

Person: Vikram Iyengar

DBLP DBLP: Iyengar:Vikram

Contributed to:

DAC 20062006
DATE 20062006
DAC 20032003
DATE 20032003
DAC 20022002
DATE 20022002

Wrote 6 papers:

DAC-2006-IyengarGT #flexibility #scalability
A flexible and scalable methodology for GHz-speed structural test (VI, GG, MT), pp. 314–319.
DATE-2006-LiuI #optimisation #scheduling #using
Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking (CL, VI), pp. 652–657.
DAC-2003-SehgalIKC #multi #reduction #using
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers (AS, VI, MDK, KC), pp. 738–743.
DATE-2003-IyengarCSC #approach #optimisation #testing #using
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization (VI, AC, SS, KC), pp. 11188–11190.
DAC-2002-IyengarCM #constraints #reduction #scheduling
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs (VI, KC, EJM), pp. 685–690.
DATE-2002-IyengarCM #performance #scalability
Efficient Wrapper/TAM Co-Optimization for Large SOCs (VI, KC, EJM), pp. 491–498.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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