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Travelled to:
1 × France
1 × USA
2 × Germany
Collaborated with:
K.Chakrabarty S.K.Goel E.J.Marinissen F.Liu S.Ozev V.Iyengar M.D.Krasniewski
Talks about:
test (4) soc (3) effici (2) core (2) use (2) tam (2) infrastructur (1) architectur (1) hierarchi (1) multipli (1)

Person: Anuja Sehgal

DBLP DBLP: Sehgal:Anuja

Contributed to:

DATE 20062006
DATE 20052005
DATE v1 20042004
DAC 20032003

Wrote 4 papers:

DATE-2006-SehgalGMC #design #framework
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips (AS, SKG, EJM, KC), pp. 285–290.
DATE-2005-SehgalLOC #testing
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores (AS, FL, SO, KC), pp. 50–55.
DATE-v1-2004-SehgalC #architecture #composition #performance #testing #using
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures (AS, KC), pp. 422–427.
DAC-2003-SehgalIKC #multi #reduction #using
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers (AS, VI, MDK, KC), pp. 738–743.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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