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Travelled to:
1 × Korea
15 × USA
8 × France
8 × Germany
Collaborated with:
A.Chandra F.Su T.Xu X.Kavousianos Y.Zhang A.Sehgal Y.Luo V.Iyengar C.Liu Q.Xu Y.Zhao E.J.Marinissen M.Yilmaz B.B.Bhattacharya F.Ye T.Ho B.M.Al-Hashimi Z.Wang W.L.Hwang M.Gössel S.Roy M.Ibrahim S.Deutsch M.Richter L.Li J.P.Hayes L.Jiang C.Liao C.H.Wen R.A.Shafik S.Bahukudumbi R.Kacprowicz Y.Zhang S.Wang N.Nicolici P.M.Rosinger V.K.Pamula R.P.Dick M.H.Tehranipour M.Nourani D.K.Pradhan N.Karimi P.Gupta S.Patil S.Balatsouka V.Tenentes K.Peng M.Tehranipoor S.K.Goel F.Liu S.Ozev M.D.Krasniewski S.Schweizer S.Kumar P.P.Chakrabarti F.Vartziotis R.A.Parekhji A.Jain B.Eklow K.Hu B.Hsu A.Madison R.B.Fair D.Mitra S.Ghoshal H.Rahaman A.Larsson E.Larsson P.Eles Z.Peng F.Xie X.Liang N.Jing
Talks about:
test (40) microfluid (18) biochip (15) digit (15) base (13) use (11) optim (10) soc (10) system (9) design (9)

Person: Krishnendu Chakrabarty

DBLP DBLP: Chakrabarty:Krishnendu

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
CASE 20122012
DAC 20122012
DATE 20122012
DATE 20112011
DAC 20102010
DATE 20102010
DATE 20092009
DAC 20082008
DATE 20082008
DAC 20072007
DATE 20072007
DAC 20062006
DATE 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DATE v1 20042004
DATE v2 20042004
DAC 20032003
DATE 20032003
DAC 20022002
DATE 20022002
DAC 20012001
DATE 20012001
DAC 20002000
DAC 19941994

Wrote 60 papers:

DAC-2015-XieLXCJJ
Jump test for metallic CNTs in CNFET-based SRAM (FX, XL, QX, KC, NJ, LJ), p. 6.
DATE-2015-IbrahimC #fault #personalisation
Error recovery in digital microfluidics for personalized medicine (MI, KC), pp. 247–252.
DATE-2015-LiaoWC #3d #manycore #online
An online thermal-constrained task scheduler for 3D multi-core processors (CHL, CHPW, KC), pp. 351–356.
DAC-2014-RoyKCBC #streaming #using
Demand-Driven Mixture Preparation and Droplet Streaming using Digital Microfluidic Biochips (SR, SK, PPC, BBB, KC), p. 6.
DATE-2014-VartziotisKCPJ #multi #optimisation #using
Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing (FV, XK, KC, RAP, AJ), pp. 1–6.
DAC-2013-JiangYXCE #3d #effectiveness #on the #performance
On effective and efficient in-field TSV repair for stacked 3D ICs (LJ, FY, QX, KC, BE), p. 6.
DAC-2013-LuoCH #design #nondeterminism
Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations (YL, KC, TYH), p. 7.
DATE-2013-DeutschC #multi #using
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels (SD, KC), pp. 1065–1070.
DATE-2013-HuHMCF #detection #fault #realtime
Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips (KH, BNH, AM, KC, RBF), pp. 559–564.
DATE-2013-KavousianosC #testing
Testing for SoCs with advanced static and dynamic power-management capabilities (XK, KC), pp. 737–742.
CASE-2012-MitraGRCB #automation
Automated path planning for washing in digital microfluidic biochips (DM, SG, HR, KC, BBB), pp. 115–120.
DAC-2012-LuoC #design
Design of pin-constrained general-purpose digital microfluidic biochips (YL, KC), pp. 18–25.
DAC-2012-YeC #3d #fault
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation (FY, KC), pp. 1024–1030.
DATE-2012-KarimiCGP #fault #generative #testing
Test generation for clock-domain crossing faults in integrated circuits (NK, KC, PG, SP), pp. 406–411.
DATE-2012-LuoCH #approach #fault #synthesis
A cyberphysical synthesis approach for error recovery in digital microfluidic biochips (YL, KC, TYH), pp. 1239–1244.
DATE-2012-RichterC #manycore #reduction
Test pin count reduction for NoC-based Test delivery in multicore SOCs (MR, KC), pp. 787–792.
DATE-2011-RoyBC
Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips (SR, BBB, KC), pp. 1059–1064.
DAC-2010-ZhaoC
Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips (YZ, KC), pp. 635–640.
DATE-2010-BalatsoukaTKC #fault #power management #testing
Defect aware X-filling for low-power scan testing (SB, VT, XK, KC), pp. 873–878.
DATE-2010-PengYTC #fault #process
High-quality pattern selection for screening small-delay defects considering process variations and crosstalk (KP, MY, MT, KC), pp. 1426–1431.
DATE-2010-ShafikAC #design #embedded #optimisation #power management
Soft error-aware design optimization of low power and time-constrained embedded systems (RAS, BMAH, KC), pp. 1462–1467.
DATE-2009-KavousianosC #fault #generative #testing
Generation of compact test sets with high defect coverage (XK, KC), pp. 1130–1135.
DATE-2009-YilmazC #detection #fault
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects (MY, KC), pp. 1488–1493.
DATE-2009-ZhaoC
Cross-contamination avoidance for droplet routing in digital microfluidic biochips (YZ, KC), pp. 1290–1295.
DAC-2008-XuC #multi
Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips (TX, KC), pp. 173–178.
DATE-2008-BahukudumbiCK #scheduling
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs (SB, KC, RK), pp. 1103–1106.
DATE-2008-LarssonLCEP #architecture #optimisation #scheduling
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns (AL, EL, KC, PE, ZP), pp. 188–193.
DAC-2007-XuC #synthesis
Integrated Droplet Routing in the Synthesis of Microfluidic Biochips (TX, KC), pp. 948–953.
DAC-2007-XuZC #architecture #fault #optimisation
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects (QX, YZ, KC), pp. 676–681.
DATE-2007-WangCW #optimisation #scheduling #testing #using
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling (ZW, KC, SW), pp. 201–206.
DATE-2007-XuC #array
A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays (TX, KC), pp. 552–557.
DAC-2006-HwangSC #array #automation #design
Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications* (WLH, FS, KC), pp. 925–930.
DATE-2006-SehgalGMC #design #framework
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips (AS, SKG, EJM, KC), pp. 285–290.
DATE-2006-SuHC #synthesis
Droplet routing in the synthesis of digital microfluidic biochips (FS, WLH, KC), pp. 323–328.
DATE-2006-WangCG #fault #formal method #probability #testing #using
Test set enrichment using a probabilistic fault model and the theory of output deviations (ZW, KC, MG), pp. 1270–1275.
DAC-2005-SuC05a #synthesis
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips (FS, KC), pp. 825–830.
DAC-2005-XuNC #constraints #design #embedded #multi #optimisation
Multi-frequency wrapper design and optimization for embedded cores under average power constraints (QX, NN, KC), pp. 123–128.
DATE-2005-LiC #analysis #clustering #hybrid #sequence
Hybrid BIST Based on Repeating Sequences and Cluster Analysis (LL, KC), pp. 1142–1147.
DATE-2005-RosingerAC #agile #generative
Rapid Generation of Thermal-Safe Test Schedules (PMR, BMAH, KC), pp. 840–845.
DATE-2005-SehgalLOC #testing
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores (AS, FL, SO, KC), pp. 50–55.
DATE-2005-SuC #configuration management #design #fault tolerance
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips (FS, KC), pp. 1202–1207.
DATE-2005-SuCP #configuration management #using
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration (FS, KC, VKP), pp. 1196–1201.
DAC-2004-ZhangDC #distributed #embedded #energy #fault tolerance #realtime
Energy-aware deterministic fault tolerance in distributed real-time embedded systems (YZ, RPD, KC), pp. 550–555.
DATE-v1-2004-SehgalC #architecture #composition #performance #testing #using
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures (AS, KC), pp. 422–427.
DATE-v2-2004-TehranipourNC #flexibility #testing
Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression (MHT, MN, KC), pp. 1284–1289.
DATE-v2-2004-ZhangC #analysis #embedded #fault tolerance #realtime #scalability
Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems (YZ, KC), pp. 1170–1175.
DAC-2003-SehgalIKC #multi #reduction #using
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers (AS, VI, MDK, KC), pp. 738–743.
DATE-2003-IyengarCSC #approach #optimisation #testing #using
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization (VI, AC, SS, KC), pp. 11188–11190.
DATE-2003-LiuC #approach #fault #identification
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis (CL, KC), pp. 10230–10237.
DATE-2003-PradhanLC #detection #fault #generative #named #novel
EBIST: A Novel Test Generator with Built-In Fault Detection Capability (DKP, CL, KC), pp. 10224–10229.
DATE-2003-ZhangC #adaptation #embedded #energy #realtime
Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems (YZ, KC), pp. 10918–10925.
DAC-2002-ChandraC #reduction #testing #using
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes (AC, KC), pp. 673–678.
DAC-2002-IyengarCM #constraints #reduction #scheduling
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs (VI, KC, EJM), pp. 685–690.
DATE-2002-ChandraC #clustering #testing
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression (AC, KC), pp. 598–603.
DATE-2002-IyengarCM #performance #scalability
Efficient Wrapper/TAM Co-Optimization for Large SOCs (VI, KC, EJM), pp. 491–498.
DATE-2002-LiuCG #identification
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment (CL, KC, MG), pp. 382–386.
DAC-2001-ChandraC #power management #testing
Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip (AC, KC), pp. 166–169.
DATE-2001-ChandraC #performance #testing #using
Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding (AC, KC), pp. 145–149.
DAC-2000-Chakrabarty #architecture #constraints #design
Design of system-on-a-chip test access architectures under place-and-route and power constraints (KC), pp. 432–437.
DAC-1994-ChakrabartyH #named #testing
DFBT: A Design-for-Testability Method Based on Balance Testing (KC, JPH), pp. 351–357.

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