BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
1 × Germany
Collaborated with:
E.Larsson M.Väyrynen P.Subramanyan K.K.Saluja
Talks about:
execut (2) toler (2) fault (2) chip (2) multiprocessor (1) processor (1) multiplex (1) techniqu (1) general (1) system (1)

Person: Virendra Singh

DBLP DBLP: Singh:Virendra

Contributed to:

DATE 20102010
DATE 20092009

Wrote 2 papers:

DATE-2010-SubramanyanSSL #execution #fault tolerance #multi #performance
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors (PS, VS, KKS, EL), pp. 1572–1577.
DATE-2009-VayrynenSL #execution #fault tolerance #multi #optimisation
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips (MV, VS, EL), pp. 484–489.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.