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Travelled to:
1 × USA
Collaborated with:
U.Golze
Talks about:
extractor (1) instruct (1) hierarch (1) circuit (1) layout (1) verif (1) reduc (1) vlsi (1) risc (1) set (1)

Person: Volker Henkel

DBLP DBLP: Henkel:Volker

Contributed to:

DAC 19881988

Wrote 1 papers:

DAC-1988-HenkelG #layout #named #set #verification
RISCE — A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification (VH, UG), pp. 465–470.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.