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Travelled to:
1 × USA
Collaborated with:
K.Khoo R.K.Brayton
Talks about:
sequenti (1) equival (1) circuit (1) clock (1) check (1) gate (1)

Person: Yu-Yun Dai

DBLP DBLP: Dai:Yu=Yun

Contributed to:

DAC 20152015

Wrote 1 papers:

DAC-2015-DaiKB #equivalence
Sequential equivalence checking of clock-gated circuits (YYD, KYK, RKB), p. 6.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.