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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
3 × USA
Collaborated with:
Y.Chang C.Chang S.Huang J.Lin H.Wang Y.Lu P.Lee H.Lee C.Chang I.Lin C.Shen
Talks about:
chip (3) clock (2) interpos (1) codesign (1) obstacl (1) multipl (1) design (1) assign (1) match (1) avoid (1)

Person: Yuan-Kai Ho

DBLP DBLP: Ho:Yuan=Kai

Contributed to:

DAC 20132013
DAC 20122012
DAC 20082008

Wrote 3 papers:

DAC-2013-HoC #multi
Multiple chip planning for chip-interposer codesign (YKH, YWC), p. 6.
DAC-2012-LeeLHCCLS #design
Obstacle-avoiding free-assignment routing for flip-chip designs (PWL, HCL, YKH, YWC, CFC, IJL, CFS), pp. 1088–1093.
Type-matching clock tree for zero skew clock gating (CMC, SHH, YKH, JZL, HPW, YSL), pp. 714–719.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.