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XHTML 1.0 W3C Rec
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Travelled to:
1 × France
1 × Germany
4 × USA
Collaborated with:
Y.Nieh C.Cheng C.Chang H.Yeh W.Tu F.Lu S.Hsu W.Yu Y.Ho J.Lin H.Wang Y.Lu
Talks about:
clock (9) period (4) minim (4) minimum (2) tree (2) skew (2) path (2) gate (2) awar (2) synthesi (1)

Person: Shih-Hsu Huang

DBLP DBLP: Huang:Shih=Hsu

Contributed to:

DATE 20142014
DATE 20132013
DAC 20082008
DAC 20072007
DAC 20062006
DAC 20052005

Wrote 7 papers:

DATE-2014-YehHN #power management
Leakage-power-aware clock period minimization (HHY, SHH, YTN), pp. 1–6.
Co-synthesis of data paths and clock control paths for minimum-period clock gating (WPT, SHH, CHC), pp. 1831–1836.
Type-matching clock tree for zero skew clock gating (CMC, SHH, YKH, JZL, HPW, YSL), pp. 714–719.
Clock Period Minimization with Minimum Delay Insertion (SHH, CHC, CMC, YTN), pp. 970–975.
Register binding for clock period minimization (SHH, CHC, YTN, WCY), pp. 439–444.
DAC-2005-HuangNL #scheduling
Race-condition-aware clock skew scheduling (SHH, YTN, FPL), pp. 475–478.
Minimizing peak current via opposite-phase clock tree (YTN, SHH, SYH), pp. 182–185.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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