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Travelled to:
1 × USA
Collaborated with:
T.Akino M.Shimode T.Negishi
Talks about:
circuit (1) inform (1) verif (1) simul (1) time (1) mask (1) base (1) mos (1) lsi (1)

Person: Yukinaga Kurashige

DBLP DBLP: Kurashige:Yukinaga

Contributed to:

DAC 19791979

Wrote 1 papers:

DAC-1979-AkinoSKN #simulation #verification
Circuit simulation and timing verification based on MOS/LSI mask information (TA, MS, YK, TN), pp. 88–94.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.