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Travelled to:
1 × USA
Collaborated with:
L.M.Huisman G.M.Silberman D.K.Beece V.S.Iyengar D.T.Tang L.S.Woo
Talks about:
simul (3) transistor (1) coverag (1) circuit (1) analysi (1) switch (1) machin (1) verif (1) logic (1) level (1)

Person: Zeev Barzilai

DBLP DBLP: Barzilai:Zeev

Contributed to:

DAC 19861986
DAC 19831983

Wrote 2 papers:

DAC-1986-BarzilaiBHIS #analysis #fault #named #performance #verification
SLS — a fast switch level simulator for verification and fault coverage analysis (ZB, DKB, LMH, VSI, GMS), pp. 164–170.
DAC-1983-BarzilaiHSTW #logic #simulation #using
Simulating pass transistor circuits using logic simulation machines (ZB, LMH, GMS, DTT, LSW), pp. 157–163.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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