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Travelled to:
3 × USA
Collaborated with:
G.Deibert G.Papp F.Villante J.Xiong C.Visweswariah V.Zolotov Y.Liu Z.Barzilai L.M.Huisman V.S.Iyengar G.M.Silberman R.K.Gupta S.Rawat S.K.Shukla B.Bailey M.Fujita C.Pixley J.O'Leary F.Somenzi
Talks about:
verif (3) engin (2) transistor (1) parametr (1) consider (1) perform (1) coverag (1) circuit (1) analysi (1) switch (1)

Person: Daniel K. Beece

DBLP DBLP: Beece:Daniel_K=

Contributed to:

DAC 20102010
DAC 20032003
DAC 19881988
DAC 19861986

Wrote 4 papers:

DAC-2010-BeeceXVZL #parametricity
Transistor sizing of custom high-performance digital circuits with parametric yield considerations (DKB, JX, CV, VZ, YL), pp. 781–786.
DAC-2003-GuptaRSBBFPOS #verification
Formal verification — prove it or pitch it (RKG, SR, SKS, BB, DKB, MF, CP, JO, FS), pp. 710–711.
DAC-1988-BeeceDPV #verification
The IBM Engineering Verification Engine (DKB, GD, GP, FV), pp. 218–224.
DAC-1986-BarzilaiBHIS #analysis #fault #named #performance #verification
SLS — a fast switch level simulator for verification and fault coverage analysis (ZB, DKB, LMH, VSI, GMS), pp. 164–170.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.