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Travelled to:
1 × USA
Collaborated with:
F.Yuan Q.Xu R.Ye W.Jone J.Zhang L.Wei
Talks about:
trust (2) placement (1) hardwar (1) generat (1) circuit (1) voltag (1) specul (1) island (1) verif (1) veri (1)

Person: Zelong Sun

DBLP DBLP: Sun:Zelong

Contributed to:

DAC 20132013

Wrote 2 papers:

DAC-2013-YeYSJX #generative
Post-placement voltage island generation for timing-speculative circuits (RY, FY, ZS, WBJ, QX), p. 6.
DAC-2013-ZhangYWSX #hardware #named #trust #verification
VeriTrust: verification for hardware trust (JZ, FY, LW, ZS, QX), p. 8.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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