Travelled to:10 × USA
4 × Germany
5 × France
Collaborated with:F.Yuan L.Huang X.Liu N.Nicolici R.Ye K.Chakrabarty L.Jiang S.Tang T.Wang J.Zhang Y.Zhang B.Eklow X.Li Y.Liu Q.Zhang W.Jone L.Wei Z.Sun Y.Liu H.Zhou J.Li Y.Hu L.Zhang Y.Han Y.Tian F.Ye F.Xie X.Liang N.Jing
Talks about:test (13) base (8) time (7) core (6) schedul (5) specul (5) framework (4) silicon (4) reliabl (4) circuit (4)
Person: Qiang Xu
DBLP: Xu:Qiang
Contributed to:
2015
201520142013201220122011201120102010200920092008200820072007200520042003Wrote 37 papers:
- DAC-2015-LiuZWYX #analysis #difference #encryption #fault #named
- DERA: yet another differential fault attack on cryptographic devices based on error rate analysis (YL, JZ, LW, FY, QX), p. 6.
- DAC-2015-XieLXCJJ
- Jump test for metallic CNTs in CNFET-based SRAM (FX, XL, QX, KC, NJ, LJ), p. 6.
- DATE-2015-YeYZX #on the
- On the premises and prospects of timing speculation (RY, FY, JZ, QX), pp. 605–608.
- DATE-2015-ZhangWTYX #approximate #framework #named #network
- ApproxANN: an approximate computing framework for artificial neural network (QZ, TW, YT, FY, QX), pp. 701–706.
- DAC-2014-WangX #on the #performance #simulation
- On the Simulation of NBTI-Induced Performance Degradation Considering Arbitrary Temperature and Voltage Variations (TW, QX), p. 6.
- DAC-2014-ZhangYYX #approximate #framework #named
- ApproxIt: An Approximate Computing Framework for Iterative Methods (QZ, FY, RY, QX), p. 6.
- DAC-2013-JiangYXCE #3d #effectiveness #on the #performance
- On effective and efficient in-field TSV repair for stacked 3D ICs (LJ, FY, QX, KC, BE), p. 6.
- DAC-2013-YeYSJX #generative
- Post-placement voltage island generation for timing-speculative circuits (RY, FY, ZS, WBJ, QX), p. 6.
- DAC-2013-YuanLJX #on the #testing
- On testing timing-speculative circuits (FY, YL, WBJ, QX), p. 6.
- DAC-2013-YuanX #fault #logic #low cost #named #scalability
- InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits (FY, QX), p. 6.
- DAC-2013-ZhangYWSX #hardware #named #trust #verification
- VeriTrust: verification for hardware trust (JZ, FY, LW, ZS, QX), p. 8.
- DAC-2012-YuanLX #configuration management #debugging #named
- X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug (FY, XL, QX), pp. 555–560.
- DATE-2012-JiangXE #3d #effectiveness #on the
- On effective TSV repair for 3D-stacked ICs (LJ, QX, BE), pp. 793–798.
- DATE-2012-YeYZX #scheduling
- Clock skew scheduling for timing speculation (RY, FY, HZ, QX), pp. 929–934.
- DAC-2011-HuangYX #multi #scheduling
- Customer-aware task allocation and scheduling for multi-mode MPSoCs (LH, RY, QX), pp. 387–392.
- DAC-2011-LiuYX #low cost
- Re-synthesis for cost-efficient circuit-level timing speculation (YL, FY, QX), pp. 158–163.
- DATE-2011-LiuX #debugging #multi #on the
- On multiplexed signal tracing for post-silicon debug (XL, QX), pp. 685–690.
- DAC-2010-HuangX #performance #process #scheduling
- Performance yield-driven task allocation and scheduling for MPSoCs under process variation (LH, QX), pp. 326–331.
- DATE-2010-HuangX #framework #named #reliability #simulation
- AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs (LH, QX), pp. 51–56.
- DATE-2010-HuangX10a #constraints #energy #multi #reliability #scheduling
- Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint (LH, QX), pp. 1584–1589.
- DATE-2010-LiuZYX #power management #pseudo #testing
- Layout-aware pseudo-functional testing for critical paths considering power supply noise effects (XL, YZ, FY, QX), pp. 1432–1437.
- DAC-2009-LiuX #design #validation
- Interconnection fabric design for tracing signals in post-silicon validation (XL, QX), pp. 352–357.
- DAC-2009-YuanX #identification #on the #pseudo #testing
- On systematic illegal state identification for pseudo-functional testing (FY, QX), pp. 702–707.
- DATE-2009-HuangYX #scheduling
- Lifetime reliability-aware task allocation and scheduling for MPSoC platforms (LH, FY, QX), pp. 51–56.
- DATE-2009-JiangHX #3d #architecture #design #optimisation
- Test architecture design and optimization for three-dimensional SoCs (LJ, LH, QX), pp. 220–225.
- DATE-2009-LiuX #validation
- Trace signal selection for visibility enhancement in post-silicon validation (XL, QX), pp. 1338–1343.
- DATE-2009-LiuX09a #framework #reduction
- A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment (XL, QX), pp. 1494–1499.
- DAC-2008-HuangYX #composition #on the #reliability #testing
- On reliable modular testing with vulnerable test access mechanisms (LH, FY, QX), pp. 834–839.
- DATE-2008-LiXHL #named #reduction #testing
- iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing (JL, QX, YH, XL), pp. 1184–1189.
- DATE-2008-TangX #debugging #transaction
- In-band Cross-Trigger Event Transmission for Transaction-Based Debug (ST, QX), pp. 414–419.
- DATE-2008-YuanHX
- Re-Examining the Use of Network-on-Chip as Test Access Mechanism (FY, LH, QX), pp. 808–811.
- DATE-2008-ZhangHXL #fault #manycore #using
- Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology (LZ, YH, QX, XL), pp. 891–896.
- DAC-2007-XuZC #architecture #fault #optimisation
- SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects (QX, YZ, KC), pp. 676–681.
- DATE-2007-TangX #debugging #framework #manycore #platform
- A multi-core debug platform for NoC-based systems (ST, QX), pp. 870–875.
- DAC-2005-XuNC #constraints #design #embedded #multi #optimisation
- Multi-frequency wrapper design and optimization for embedded cores under average power constraints (QX, NN, KC), pp. 123–128.
- DATE-v1-2004-XuN #design #multi #testing
- Wrapper Design for Testing IP Cores with Multiple Clock Domains (QX, NN), pp. 416–421.
- DATE-2003-XuN #fault #testing
- Delay Fault Testing of Core-Based Systems-on-a-Chi (QX, NN), pp. 10744–10752.