BibSLEIGH corpus
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Travelled to:
1 × Germany
Collaborated with:
Talks about:
transient (1) nonlinear (1) circuit (1) robust (1) analog (1) simul (1) fault (1) fast (1)

Person: Zheng Rong Yang

DBLP DBLP: Yang:Zheng_Rong

Contributed to:

DATE 19991999

Wrote 1 papers:

DATE-1999-YangZ #fault #performance #robust #simulation
Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits (ZRY, MZ), pp. 244–248.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.