21 papers:
DAC-2015-GuoWHWLC #design #latency #named #novel #reduction- FlexLevel: a novel NAND flash storage system design for LDPC latency reduction (JG, WW, JH, DW, HL, YC), p. 6.
- DAC-2014-LiuCYLHL #fault #locality #named
- EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs (RSL, MYC, CLY, CHL, KCH, HPL), p. 6.
ICPR-2014-MarroccoT #fault- Bit Error Recovery in ECOC Systems through LDPC Codes (CM, FT), pp. 1454–1459.
DATE-2012-CondoMM #architecture- A Network-on-Chip-based turbo/LDPC decoder architecture (CC, MM, GM), pp. 1525–1530.
STOC-2012-KaufmanL #graph #symmetry #transitive- Edge transitive ramanujan graphs and symmetric LDPC good codes (TK, AL), pp. 359–366.
- DATE-2011-MurugappaABJ #architecture #flexibility #multi #throughput
- A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding (PM, RAK, AB, MJ), pp. 228–233.
- DAC-2009-AmadorPR #architecture #memory management #problem
- Optimum LDPC decoder: a memory architecture problem (EA, RP, VR), pp. 891–896.
- DATE-2009-0004SKAKW #novel
- A novel LDPC decoder for DVB-S2 IP (SM, MS, MK, MA, FK, NW), pp. 1308–1313.
- DATE-2009-ChenKLA
- Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing (XC, JK, SL, VA), pp. 1530–1535.
- DAC-2008-MoussaBJ #flexibility #multi #network
- Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder (HM, AB, MJ), pp. 429–434.
- DATE-2008-MayAW #case study #design
- A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder (MM, MA, NW), pp. 456–461.
PPoPP-2008-FernandesSS #gpu #parallel- Massive parallel LDPC decoding on GPU (GFPF, LS, VMMdS), pp. 83–90.
- DATE-2007-BrackALKWLRRF #complexity #generative #standard
- Low complexity LDPC code decoders for next generation standards (TB, MA, TLE, FK, NW, NEL, FR, MR, LF), pp. 331–336.
- DATE-2007-DielissenH #implementation #parallel
- Non-fractional parallelism in LDPC decoder implementations (JD, AH), pp. 337–342.
- DATE-2007-WangC #energy #mobile #realtime
- Minimum-energy LDPC decoder for real-time mobile application (WW, GC), pp. 343–348.
- DATE-2006-BrackKW #design
- Disclosing the LDPC code decoder design space (TB, FK, NW), pp. 200–205.
- DATE-DF-2006-DielissenHB #low cost
- Low cost LDPC decoder for DVB-S2 (JD, AH, VB), pp. 130–135.
- DATE-DF-2006-QuaglioVCTM #flexibility #framework
- Interconnection framework for high-throughput, flexible LDPC decoders (FQ, FV, CC, AT, GM), pp. 124–129.
- DAC-2005-UrardPGMLYG
- A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3) (PU, LP, PG, TM, VL, EY, BG), pp. 547–548.
- DATE-2005-KienleBW
- A Synthesizable IP Core for DVB-S2 LDPC Code Decoding (FK, TB, NW), pp. 100–105.
- DATE-DF-2004-CoccoDHHH #architecture #scalability
- A Scalable Architecture for LDPC Decodin (MC, JD, MJMH, AH, JH), pp. 88–95.
