BibSLEIGH — Layout Techniques for Minimizing On-Chip Interconnect Self Inductance

Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob White
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
DAC, 1998.

DAC 1998

@inproceedings{DAC-1998-MassoudMBW,
	author        = "Yehia Massoud and Steve S. Majors and Tareq Bustami and Jacob White",
	booktitle     = "{Proceedings of the 35th Design Automation Conference}",
	doi           = "10.1145/277044.277194",
	isbn          = "0-89791-964-5",
	pages         = "566--571",
	publisher     = "{ACM Press}",
	title         = "{Layout Techniques for Minimizing On-Chip Interconnect Self Inductance}",
	year          = 1998,
}

Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob WhiteLayout Techniques for Minimizing On-Chip Interconnect Self InductanceDAC, 1998.

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Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob White
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
DAC, 1998.