BibSLEIGH corpus
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Used together with:
time (7)
circuit (4)
high (4)
lock (4)
model (4)

Stem jitter$ (all stems)

22 papers:

DATEDATE-2014-HaddadTBF #independence #modelling #on the #probability
On the assumption of mutual independence of jitter realizations in P-TRNG stochastic models (PH, YT, FB, VF), pp. 1–6.
DATEDATE-2013-TzouBHC #bound #composition #using
Periodic jitter and bounded uncorrelated jitter decomposition using incoherent undersampling (NT, DB, SWH, AC), pp. 1667–1672.
HCIHCI-UC-2013-AminJGMS #impact analysis #latency #quality
Assessing the Impact of Latency and Jitter on the Perceived Quality of Call of Duty Modern Warfare 2 (RA, FJ, JEG, JM, TS), pp. 97–106.
DATEDATE-2012-NarayananDZT #design #using #verification
Verifying jitter in an analog and mixed signal design using dynamic time warping (RN, AD, MHZ, ST), pp. 1413–1416.
DACDAC-2011-YinKL #effectiveness
High effective-resolution built-in jitter characterization with quantization noise shaping (LY, YK, PL), pp. 765–770.
DATEDATE-2011-ErbP #analysis #performance
A method for fast jitter tolerance analysis of high-speed PLLs (SE, WP), pp. 1107–1112.
DATEDATE-2010-LeeYCC #embedded #metric
An embedded wide-range and high-resolution CLOCK jitter measurement circuit (YL, CYY, NCDC, JJC), pp. 1637–1640.
DACDAC-2009-BurnhamYH #probability
A stochastic jitter model for analyzing digital timing-recovery circuits (JRB, CKKY, HAH), pp. 116–121.
CASECASE-2008-Pohjola #adaptation
Adaptive jitter margin PID controller (MP), pp. 534–539.
DATEDATE-2008-ChoiC #testing #using
Digital bit stream jitter testing using jitter expansion (HWC, AC), pp. 1468–1473.
DATEDATE-2008-KeezerMD #injection #multi
Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications (DCK, DM, PD), pp. 1486–1491.
DACDAC-2007-ChanZ #modelling
Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops (HHYC, ZZ), pp. 430–435.
DACDAC-2007-PimentelP #analysis
Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application (JRP, JP), pp. 290–293.
DATEDATE-2007-BarajasCCMGCBI #behaviour #interactive #modelling #optimisation
Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems (EB, RC, DC, DM, JLG, IC, SB, MI), pp. 1430–1435.
DATEDATE-2007-KeezerMD #multi
Method for reducing jitter in multi-gigahertz ATE (DCK, DM, PD), pp. 701–706.
DACDAC-2006-ZouMGS #optimisation
A CPPLL hierarchical optimization methodology considering jitter, power and locking time (JZ, DM, HEG, US), pp. 19–24.
DACDAC-2005-Vasudevan #simulation
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits (VV), pp. 397–402.
DATEDATE-v1-2004-OngHCW #multi #random
Random Jitter Extraction Technique in a Multi-Gigahertz Signal (CKO, DH, KTC, LCW), pp. 286–291.
Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators (PH), pp. 532–537.
DACDAC-2003-ManeatisKMMS #generative #multi #self
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL (JGM, JK, IM, JM, MS), pp. 688–690.
DATEDATE-2003-GouraryRUZGM #approach #approximate
Approximation Approach for Timing Jitter Characterization in Circuit Simulators (MMG, SGR, SLU, MMZ, KKG, BJM), pp. 10156–10161.
DATEDATE-2000-GouraryRUZGM #approach
A New Approach for Computation of Timing Jitter in Phase Locked Loops (MMG, SGR, SLU, MMZ, KKG, BJM), pp. 345–349.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.