S. Raja, F. Varadi, Murat R. Becer, Joao Geada
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
DAC, 2008.
@inproceedings{DAC-2008-RajaVBG,
author = "S. Raja and F. Varadi and Murat R. Becer and Joao Geada",
booktitle = "{Proceedings of the 45th Design Automation Conference}",
doi = "10.1145/1391469.1391588",
isbn = "978-1-60558-115-6",
pages = "456--461",
publisher = "{ACM}",
title = "{Transistor level gate modeling for accurate and fast timing, noise, and power analysis}",
year = 2008,
}