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Travelled to:
1 × USA
Collaborated with:
S.Raja F.Varadi M.R.Becer
Talks about:
transistor (1) analysi (1) power (1) model (1) level (1) accur (1) time (1) nois (1) gate (1) fast (1)

Person: Joao Geada

DBLP DBLP: Geada:Joao

Contributed to:

DAC 20082008

Wrote 1 papers:

DAC-2008-RajaVBG #analysis #modelling #performance
Transistor level gate modeling for accurate and fast timing, noise, and power analysis (SR, FV, MRB, JG), pp. 456–461.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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