BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × USA
Collaborated with:
F.Varadi M.R.Becer J.Geada
Talks about:
transistor (1) analysi (1) power (1) model (1) level (1) accur (1) time (1) nois (1) gate (1) fast (1)

Person: S. Raja

DBLP DBLP: Raja:S=

Contributed to:

DAC 20082008

Wrote 1 papers:

DAC-2008-RajaVBG #analysis #modelling #performance
Transistor level gate modeling for accurate and fast timing, noise, and power analysis (SR, FV, MRB, JG), pp. 456–461.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.