BibSLEIGH — A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits

Oscar Garnica, Juan Lanchares, Román Hermida
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits
DATE, 2001.

DATE 2001

@inproceedings{DATE-2001-GarnicaLH,
	author        = "Oscar Garnica and Juan Lanchares and Román Hermida",
	booktitle     = "{Proceedings of the Sixth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1145/367072.368013",
	isbn          = "0-7695-0993-2",
	pages         = "810",
	publisher     = "{ACM}",
	title         = "{A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits}",
	year          = 2001,
}

Oscar Garnica, Juan Lanchares, Román HermidaA pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuitsDATE, 2001.

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Oscar Garnica, Juan Lanchares, Román Hermida
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits
DATE, 2001.