Travelled to:
1 × France
1 × Germany
Collaborated with:
O.Garnica R.Hermida J.I.Hidalgo J.M.Colmenar R.Baraglia F.Tirado J.d.Vicente N.Morón R.Perego S.López M.Prieto
Talks about:
asynchron (3) algorithm (2) parallel (2) compact (2) model (2) genet (2) delay (2) fpga (2) thermodynam (1) combinatori (1)
Person: Juan Lanchares
DBLP: Lanchares:Juan
Contributed to:
Wrote 6 papers:
- PDP-2008-ColmenarMGLH #modelling #probability #using
- Modelling Asynchronous Systems using Probability Distribution Functions (JMC, NM, OG, JL, JIH), pp. 3–11.
- PDP-2004-ColmenarGLHLH #empirical #latency #pipes and filters
- Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays (JMC, OG, SL, JIH, JL, RH), pp. 112–119.
- PDP-2003-HidalgoPLBTG #algorithm #hybrid #parallel #search-based
- Hybrid Parallelization of a Compact Genetic Algorithm (JIH, MP, JL, RB, FT, OG), pp. 449–455.
- DATE-2002-VicenteLH #combinator #optimisation
- FPGA Placement by Thermodynamic Combinatorial Optimization (JdV, JL, RH), pp. 54–60.
- DATE-2001-GarnicaLH #power management #pseudo
- A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits (OG, JL, RH), p. 810.
- PDP-2001-BaragliaPHLT #algorithm #clustering #parallel #search-based
- A Parallel Compact Genetic Algorithm for Multi-FPGA Partitioning (RB, RP, JIH, JL, FT), pp. 113–120.