BibSLEIGH — Roman

Travelled to:

1 × USA
6 × France
6 × Germany

Collaborated with:

J.M.Mendías M.C.Molina R.Ruiz-Sautua J.Lanchares J.M.Mendias A.A.D.Barrio S.O.Memik O.Garnica M.Fernández N.Bagherzadeh M.Sanchez-Elez O.Peñalba R.Maestre F.J.Kurdahi J.d.Vicente J.A.Maestro D.Mozos N.Genko D.Atienza G.D.Micheli F.Catthoor J.M.Colmenar S.López J.I.Hidalgo M.L.Anido H.Du H.Singh

Talks about:

synthesi (8) level (8) high (7) data (5) circuit (4) optim (4) reconfigur (3) schedul (3) multipl (3) multi (3)

Person: Román Hermida

DBLP: Hermida:Rom=aacute=n

Contributed to:

2013

2011

2010

2007

2006

2005

2004

2003

2002

2001

1999

1998

Wrote 20 papers:

DATE-2013-BarrioHMMM #multi #synthesis: Multispeculative additive trees in high-level synthesis (AADB, RH, SOM, JMM, MCM), pp. 188–193.
DATE-2011-BarrioMMMH #optimisation: Power optimization in heterogenous datapaths (AADB, SOM, MCM, JMM, RH), pp. 1400–1405.
DATE-2010-BarrioMMHM #functional #synthesis #using: Using Speculative Functional Units in high level synthesis (AADB, MCM, JMM, RH, SOM), pp. 1779–1784.
DATE-2007-MolinaRMH #multi #optimisation #synthesis: Area optimization of multi-cycle operators in high-level synthesis (MCM, RRS, JMM, RH), pp. 449–454.
DATE-2006-Ruiz-SautuaMMH #multi #optimisation #performance: Pre-synthesis optimization of multiplications to improve circuit performance (RRS, MCM, JMM, RH), pp. 1306–1311.
DATE-2005-GenkoAMMHC #framework: A Complete Network-On-Chip Emulation Framework (NG, DA, GDM, JMM, RH, FC), pp. 246–251.
DATE-2005-Ruiz-SautuaMMH #behaviour #performance #synthesis: Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis (RRS, MCM, JMM, RH), pp. 1252–1257.
DATE-v1-2004-MolinaRMH #behaviour #scheduling: Behavioural Bitwise Scheduling Based on Computational Effort Balancing (MCM, RRS, JMM, RH), pp. 684–685.
PDP-2004-ColmenarGLHLH #empirical #latency #pipes and filters: Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays (JMC, OG, SL, JIH, JL, RH), pp. 112–119.
DATE-2003-MolinaMH #hardware: High-Level Allocation to Minimize Internal Hardware Wastage (MCM, JMM, RH), pp. 10264–10269.
DATE-2003-Sanchez-ElezFADBH #architecture #configuration management #data transformation #energy #memory management #multi: Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures (MSE, MF, MLA, HD, NB, RH), pp. 10036–10043.
DAC-2002-MolinaMH #multi #synthesis: High-level synthesis of multiple-precision circuitsindependent of data-objects length (MCM, JMM, RH), pp. 612–615.
DATE-2002-MolinaMH #independence #multi: Multiple-Precision Circuits Allocation Independent of Data-Objects Length (MCM, JMM, RH), pp. 909–913.
DATE-2002-PenalbaMH #reuse: Maximizing Conditonal Reuse by Pre-Synthesis Transformations (OP, JMM, RH), p. 1097.
DATE-2002-Sanchez-ElezFMMKHB #architecture #configuration management #multi: A Complete Data Scheduler for Multi-Context Reconfigurable Architectures (MSE, MF, RM, RH, NB, FJK), pp. 547–552.
DATE-2002-VicenteLH #combinator #optimisation: FPGA Placement by Thermodynamic Combinatorial Optimization (JdV, JL, RH), pp. 54–60.
DATE-2001-GarnicaLH #power management #pseudo: A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits (OG, JL, RH), p. 810.
DATE-1999-MaestreKBSHF #configuration management #kernel #scheduling: Kernel Scheduling in Reconfigurable Computing (RM, FJK, NB, HS, RH, MF), pp. 90–96.
DATE-1999-MaestroMH #approach #hardware #problem: The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach (JAM, DM, RH), pp. 766–767.
DATE-1998-MendiasH #formal method #perspective #synthesis: Correct High-Level Synthesis: a Formal Perspective (JMM, RH), pp. 977–978.