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Travelled to:
1 × India
2 × USA
Collaborated with:
A.Roth S.Nagarakatte S.J.Battle M.Hempstead
Talks about:
toler (2) order (2) processor (1) flexibl (1) regist (1) latenc (1) execut (1) energi (1) effici (1) refer (1)

Person: Andrew D. Hilton

DBLP DBLP: Hilton:Andrew_D=

Contributed to:

HPCA 20122012
HPCA 20102010
HPCA 20092009

Wrote 3 papers:

HPCA-2012-BattleHHR #flexibility #using
Flexible register management using reference counting (SJB, ADH, MH, AR), pp. 273–284.
HPCA-2010-HiltonR #energy #execution #named
BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution (ADH, AR), pp. 1–12.
HPCA-2009-HiltonNR #named
iCFP: Tolerating all-level cache misses in in-order processors (ADH, SN, AR), pp. 431–442.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.