Matthew T. Jacob, Chita R. Das, Pradip Bose
Proceedings of the 16th International Conference on High-Performance Computer Architecture
HPCA, 2010.

@proceedings{HPCA-2010,
	address       = "Bangalore, India",
	editor        = "Matthew T. Jacob and Chita R. Das and Pradip Bose",
	ee            = "http://www.computer.org/csdl/proceedings/hpca/2010/5658/00/index.html",
	isbn          = "978-1-4244-5659-8",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the 16th International Conference on High-Performance Computer Architecture}",
	year          = 2010,
}

Contents (39 items)

12 ×#named
9 ×#performance
8 ×#architecture
5 ×#energy
5 ×#multi
4 ×#scalability
3 ×#execution
3 ×#memory management
3 ×#using
2 ×#adaptation

HPCA-2010-AbellaCVCG

High-Performance low-vcc in-order core (JA, PC, XV, JC, AG), pp. 1–11.

HPCA-2010-Agerwala #challenge

Exascale computing: The challenges and opportunities in the next decade (TA), p. 1.

HPCA-2010-Arvind #hardware #question

Is hardware innovation over? (A), p. 1.

HPCA-2010-BiCG #interactive #named #on-demand #performance

IADVS: On-demand performance for interactive applications (MB, IC, CG), pp. 1–10.

HPCA-2010-BiDG #energy

Delay-Hiding energy management mechanisms for DRAM (MB, RD, CG), pp. 1–10.

HPCA-2010-BiswasRMACJPPS #metric #using

Explaining cache SER anomaly using DUE AVF measurement (AB, CR, SSM, VA, LC, AJ, AEP, MP, NS), pp. 1–12.

HPCA-2010-ChampagneL #architecture #scalability

Scalable architectural support for trusted software (DC, RBL), pp. 1–12.

HPCA-2010-DongYLLTG #network #performance

High performance network virtualization with SR-IOV (YD, XY, XL, JL, KT, HG), pp. 1–10.

HPCA-2010-DoudalisP #execution #hardware #named

HARE: Hardware assisted reverse execution (ID, MP), pp. 1–12.

HPCA-2010-FarooqCJ #predict

Value Based BTB Indexing for indirect jump prediction (MUF, LC, LKJ), pp. 1–11.

HPCA-2010-GenbruggeEE #abstraction #architecture #simulation

Interval simulation: Raising the level of abstraction in architectural simulation (DG, SE, LE), pp. 1–12.

HPCA-2010-GreskampKT #configuration management #multi #named #performance #thread

LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores (BG, URK, JT), pp. 1–12.

HPCA-2010-HiltonR #energy #execution #named

BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution (ADH, AR), pp. 1–12.

HPCA-2010-HuangSWSXM #named #permutation

SIF: Overcoming the limitations of SIMD devices via implicit permutation (LH, LS, ZW, WS, NX, SM), pp. 1–12.

HPCA-2010-JafriTV #named #transaction

LiteTM: Reducing transactional state overhead (SARJ, MT, TNV), pp. 1–12.

HPCA-2010-JiangMZUIMNSB #adaptation #named #platform

CHOP: Adaptive filter-based DRAM caching for CMP server platforms (XJ, NM, LZ, MU, RI, SM, DN, YS, RB), pp. 1–12.

HPCA-2010-KahngKKS #design #reliability #trade-off

Designing a processor from the ground up to allow voltage/reliability tradeoffs (ABK, SK, RK, JS), pp. 1–11.

HPCA-2010-KaseridisSCJ #resource management #scalability #using

A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems (DK, JS, JC, LKJ), pp. 1–11.

HPCA-2010-KimHMH #algorithm #memory management #multi #named #scalability #scheduling

ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (YK, DH, OM, MHB), pp. 1–12.

HPCA-2010-KunduRDZ #modelling #performance

Application performance modeling in a virtualized environment (SK, RR, KD, MZ), pp. 1–10.

HPCA-2010-LeeCC #multi #named #performance

StimulusCache: Boosting performance of chip multiprocessors with excess cache (HL, SC, BRC), pp. 1–12.

HPCA-2010-LeeLSKKS #clustering #manycore

COMIC++: A software SVM system for heterogeneous multicore accelerator clusters (JL, JL, SS, JK, SK, ZS), pp. 1–12.

HPCA-2010-LiBKKRH #architecture #manycore #operating system

Operating system support for overlapping-ISA heterogeneous multi-core architectures (TL, PB, RCK, DAK, DR, SH), pp. 1–12.

HPCA-2010-LiuJS #clustering #comprehension #how #memory management #multi #performance

Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance (FL, XJ, YS), pp. 1–12.

HPCA-2010-MerinoPG #adaptation #architecture #low cost #named

ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture (JM, VP, JÁG), pp. 1–10.

HPCA-2010-MillerKKGBCEA #distributed #named #parallel

Graphite: A distributed parallel simulator for multicores (JEM, HK, GK, CGI, NB, CC, JE, AA), pp. 1–12.

HPCA-2010-PanKM #energy #named

FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar (YP, JK, GM), pp. 1–12.

HPCA-2010-QureshiFL #performance

Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing (MKQ, MF, LALM), pp. 1–11.

HPCA-2010-RomanescuLSB #protocol

UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all (BFR, ARL, DJS, AB), pp. 1–12.

HPCA-2010-SunJCNXCL #architecture #energy #hybrid #performance

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement (GS, YJ, YC, DN, YX, YC, HL), pp. 1–12.

HPCA-2010-TangBHC #architecture #cpu #performance #using

DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance (DT, YB, WH, MC), pp. 1–12.

HPCA-2010-TorrellasGSMO #challenge

Extreme scale computing: Challenges and opportunities (JT, BG, VS, JHM, KO), p. 1.

HPCA-2010-UdipiMB #energy #network #scalability #towards

Towards scalable, energy-efficient, bus-based on-chip networks (ANU, NM, RB), pp. 1–12.

HPCA-2010-VasanSSSS #empirical

Worth their watts? — an empirical study of datacenter servers (AV, AS, VS, TS, RS), pp. 1–10.

HPCA-2010-VujicGCRMA #on the fly

DMA++: on the fly data realignment for on-chip memories (NV, MG, FC, AR, XM, EA), pp. 1–12.

HPCA-2010-WareRFBRRC #approach #architecture #power management

Architecting for power management: The IBM POWER7TM approach (MSW, KR, MSF, BB, JCR, FLRI, JBC), pp. 1–11.

HPCA-2010-WooSLL #3d #architecture #memory management

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth (DHW, NHS, DLL, HHSL), pp. 1–12.

HPCA-2010-XekalakisC #branch #execution #multi

Handling branches in TLS systems with Multi-Path Execution (PX, MC), pp. 1–12.

HPCA-2010-XuZZY #throughput

Simple virtual channel allocation for high throughput and high frequency on-chip routers (YX, BZ, YZ, JY), pp. 1–11.