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Travelled to:
2 × Germany
Collaborated with:
G.G.E.Gielen W.Schoenmaker M.Matthes S.Baumanns C.Tischendorf R.Janssen
Talks about:
integr (2) substrat (1) inductor (1) boundari (1) conduct (1) circuit (1) signal (1) design (1) captur (1) analog (1)

Person: Bart De Smedt

DBLP DBLP: Smedt:Bart_De

Contributed to:

DATE 20122012
DATE 20032003

Wrote 2 papers:

DATE-2012-SchoenmakerMSBTJ #scalability #simulation
Large signal simulation of integrated inductors on semi-conducting substrates (WS, MM, BDS, SB, CT, RJ), pp. 1221–1226.
DATE-2003-SmedtG #bound #design #named
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits (BDS, GGEG), pp. 10256–10263.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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