BibSLEIGH — Proceedings of the 16th Conference and Exhibition on Design, Automation and Test in Europe

Wolfgang Rosenstiel, Lothar Thiele
Proceedings of the 16th Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2012.

SYS

@proceedings{DATE-2012,
	acmid         = "2492708",
	address       = "Dresden, Germany",
	editor        = "Wolfgang Rosenstiel and Lothar Thiele",
	isbn          = "978-1-4577-2145-8",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the 16th Conference and Exhibition on Design, Automation and Test in Europe}",
	year          = 2012,
}

Contents (307 items)

DATE-2012-Meder #challenge #mobile: The mobile society — chances and challenges for micro- and power electronics (KM), p. 1.
DATE-2012-Chian #industrial #modelling: New foundry models — accelerations in transformations of the semiconductor industry (MC), p. 2.
DATE-2012-QinM #automation #generative #protocol #testing: Automated generation of directed tests for transition coverage in cache coherence protocols (XQ, PM), pp. 3–8.
DATE-2012-RamboHS #consistency #memory management #multi #on the #verification: On ESL verification of memory consistency for system-on-chip multiprocessing (EAR, OPH, LCVdS), pp. 9–14.
DATE-2012-KatzRZ #csp #generative #using: Generating instruction streams using abstract CSP (YK, MR, AZ), pp. 15–20.
DATE-2012-StripfKB #approximate #architecture: A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture (TS, RK, JB), pp. 21–26.
DATE-2012-GaoWHZL #clustering #concurrent #debugging #manycore: A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems (JG, JW, YH, LZ, XL), pp. 27–32.
DATE-2012-ChenLMABJ #3d #architecture #in memory #memory management #modelling #named: CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory (KC, SL, NM, JHA, JBB, NPJ), pp. 33–38.
DATE-2012-StipicTZCUV #data access #hardware #metadata #named #performance: TagTM — accelerating STMs with hardware tags for fast meta-data access (SS, ST, FZ, AC, OSÜ, MV), pp. 39–44.
DATE-2012-ChenCHLLPR #configuration management #design #energy #hybrid: Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design (YTC, JC, HH, BL, CL, MP, GR), pp. 45–50.
DATE-2012-GomonyWAWG #mobile #realtime: DRAM selection and configuration for real-time mobile systems (MDG, CW, BA, NW, KG), pp. 51–56.
DATE-2012-RoxEG #analysis #design #network #using: Using timing analysis for the design of future switched based Ethernet automotive networks (JR, RE, PG), pp. 57–62.
DATE-2012-ZhangWHY #algorithm #energy #game studies #resource management: Fair energy resource allocation by minority game algorithm for smart buildings (CZ, WW, HH, HY), pp. 63–68.
DATE-2012-SchmutzlerSB #on the: On demand dependent deactivation of automotive ECUs (CS, MS, JB), pp. 69–74.
DATE-2012-MagnoMBPOB #network #power management: Smart power unit with ultra low power radio trigger capabilities for wireless sensor networks (MM, SJM, DB, EMP, BO, LB), pp. 75–80.
DATE-2012-MiryalaCMP #analysis #network: IR-drop analysis of graphene-based power distribution networks (SM, AC, EM, MP), pp. 81–86.
DATE-2012-HuangHLLLG #power management: Off-path leakage power aware routing for SRAM-based FPGAs (KH, YH, XL, BL, HL, JG), pp. 87–92.
DATE-2012-MakosiejTVA #design #embedded #optimisation #power management: Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization (AM, OT, AV, AA), pp. 93–98.
DATE-2012-RahmanS #power management: Post-synthesis leakage power minimization (MR, CS), pp. 99–104.
DATE-2012-MarongiuBB #clustering #embedded #lightweight #parallel #performance: Fast and lightweight support for nested parallelism on cluster-based embedded many-cores (AM, PB, LB), pp. 105–110.
DATE-2012-AnagnostopoulosBKS #distributed #divide and conquer #manycore #platform #runtime: A divide and conquer based distributed run-time mapping methodology for many-core platforms (IA, AB, GK, DS), pp. 111–116.
DATE-2012-LinC #adaptation #garbage collection: Dual Greedy: Adaptive garbage collection for page-mapping solid-state disks (WHL, LPC), pp. 117–122.
DATE-2012-MarinissenVGHRMB #detection #process: EDA solutions to new-defect detection in advanced process technologies (EJM, GV, SKG, FH, JR, NM, SB), pp. 123–128.
DATE-2012-TorresAGPR #benchmark #metric: Beyond CMOS — benchmarking for future technologies (CMST, JA, MWMG, RMP, WR), pp. 129–134.
DATE-2012-LuMS #abstraction #modelling #prototype #transaction: Accurately timed transaction level models for virtual prototyping at high abstraction level (KL, DMG, US), pp. 135–140.
DATE-2012-ChenHD #design #parallel #simulation: Out-of-order parallel simulation for ESL design (WC, XH, RD), pp. 141–146.
DATE-2012-LinWCCCHYS #analysis #functional #mutation testing #probability: A probabilistic analysis method for functional qualification under Mutation Analysis (HYL, CYW, SCC, YCC, HMC, CYH, YCY, CCS), pp. 147–152.
DATE-2012-MammoCPNZMB #approximate #simulation: Approximating checkers for simulation acceleration (BM, DC, DP, AN, AZ, RM, VB), pp. 153–158.
DATE-2012-Steinbach #guidelines #modelling: Guidelines for model based systems engineering (DS), pp. 159–160.
DATE-2012-BattezzatiCMS #algorithm #architecture #industrial #novel: SURF algorithm in FPGA: A novel architecture for high demanding industrial applications (NB, SC, MM, LS), pp. 161–162.
DATE-2012-HammamiLB #named #network #verification: NOCEVE: Network on chip emulation and verification environment (OH, XL, JMB), pp. 163–164.
DATE-2012-SassoneCMMPGMBR #dependence #network: Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks (AS, AC, AM, EM, MP, RG, VM, EB, SR), pp. 165–166.
DATE-2012-YipHI #3d #challenge #design #verification: Challenges in verifying an integrated 3D design (TGY, CYH, VI), pp. 167–168.
DATE-2012-WangXPKCP #energy #hybrid #migration #multi: Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systems (YW, QX, MP, YK, NC, MP), pp. 169–174.
DATE-2012-AksanliRM #energy #network: Benefits of green energy and proportionality in high speed wide area networks connecting data centers (BA, TSR, IM), pp. 175–180.
DATE-2012-BartoliniSFCB #energy #performance #scalability: Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer (AB, MS, JNF, AKC, LB), pp. 181–186.
DATE-2012-LiuFQ #framework #manycore #platform: Neighbor-aware dynamic thermal management for multi-core platform (GL, MF, GQ), pp. 187–192.
DATE-2012-YangGBSC #game studies #graph #policy #resource management: Playing games with scenario- and resource-aware SDF graphs through policy iteration (YY, MG, TB, SS, HC), pp. 194–199.
DATE-2012-RajeevMR #architecture #constraints #distributed #embedded #verification: Verifying timing synchronization constraints in distributed embedded architectures (ACR, SM, SR), pp. 200–205.
DATE-2012-NataleZ #finite #implementation #state machine: Task implementation of synchronous finite state machines (MDN, HZ), pp. 206–211.
DATE-2012-GuglielmoGFP #design #embedded #modelling #verification: Enabling dynamic assertion-based verification of embedded software through model-driven design (GDG, LDG, FF, GP), pp. 212–217.
DATE-2012-FirouziKT: NBTI mitigation by optimized NOP assignment and insertion (FF, SK, MBT), pp. 218–223.
DATE-2012-PontesCV #design #reliability: An accurate Single Event Effect digital design flow for reliable system level design (JJHP, NC, PV), pp. 224–229.
DATE-2012-Shahid #estimation #performance: Cross entropy minimization for efficient estimation of SRAM failure rate (MAS), pp. 230–235.
DATE-2012-YordanovAGGCBHBD #biology #verification: Experimentally driven verification of synthetic biological circuits (BY, EA, RG, EAG, SBC, SB, TH, CB, DD), pp. 236–241.
DATE-2012-Hassoun #automation #biology #design #search-based: Genetic/bio design automation for (re-)engineering biological systems (SH), pp. 242–247.
DATE-2012-ThachTKI #estimation #performance: Fast cycle estimation methodology for instruction-level emulator (DT, YT, SK, AI), pp. 248–251.
DATE-2012-DenizSH #embedded #manycore #verification: Verification coverage of embedded multicore applications (ED, AS, JH), pp. 252–255.
DATE-2012-SinghNL #generative #smt #testing: Hazard driven test generation for SMT processors (PS, VN, DLL), pp. 256–259.
DATE-2012-WangW #memory management: Extending the lifetime of NAND flash memory by salvaging bad blocks (CW, WFW), pp. 260–263.
DATE-2012-KwonKKYL #case study #in memory #memory management #ram: A case study on the application of real phase-change RAM to main memory subsystem (SK, DK, YK, SY, SL), pp. 264–267.
DATE-2012-SahlbachWE: A high-performance dense block matching solution for automotive 6D-vision (HS, SW, RE), pp. 268–271.
DATE-2012-RofoueiGPM #energy #optimisation: Optimization intensive energy harvesting (MR, MAG, MP, AMN), pp. 272–275.
DATE-2012-MilbredtGLST #approach #architecture #design: Designing FlexRay-based automotive architectures: A holistic OEM approach (PM, MG, ML, AS, JT), pp. 276–279.
DATE-2012-WernerOGHB #configuration management #distributed #manycore: Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems (SW, OO, DG, MH, JB), pp. 280–283.
DATE-2012-BathenDNG #memory management #named #variability: VaMV: Variability-aware Memory Virtualization (LADB, NDD, AN, PG), pp. 284–287.
DATE-2012-JovicYMELA #hybrid #simulation: Hybrid simulation for extensible processor cores (JJ, SY, LGM, JFE, RL, GA), pp. 288–291.
DATE-2012-PoulosYAVL #debugging #functional: Leveraging reconfigurability to raise productivity in FPGA functional debug (ZP, YSY, JA, AGV, BL), pp. 292–295.
DATE-2012-BeckerDFMPV #embedded #evolution #modelling #named #scalability #verification: MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolution (MB, GBD, FF, WM, GP, SV), pp. 296–299.
DATE-2012-WangRR #energy #runtime: Run-time power-gating in caches of GPUs for leakage energy savings (YW, SR, NR), pp. 300–303.
DATE-2012-Sun #automation #embedded #functional #generative #modelling: Automatic generation of functional models for embedded processor extensions (FS), pp. 304–307.
DATE-2012-PeranandamRSYGR #generative #modelling #testing: An integrated test generation tool for enhanced coverage of Simulink/Stateflow models (PP, SR, MS, AY, AAG, SR), pp. 308–311.
DATE-2012-LafayePBGF #embedded #modelling #resource management #simulation: Model driven resource usage simulation for critical embedded systems (ML, LP, EB, MG, DF), pp. 312–315.
DATE-2012-LiH #analysis #logic #named #performance #reliability: RAG: An efficient reliability analysis of logic circuits on graphics processing units (ML, MSH), pp. 316–319.
DATE-2012-EbrahimiDLPT #algorithm #network: CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks (ME, MD, PL, JP, HT), pp. 320–325.
DATE-2012-BhardwajCR #algorithm: An MILP-based aging-aware routing algorithm for NoCs (KB, KC, SR), pp. 326–331.
DATE-2012-AkbariSFB #3d #low cost #named #performance #reliability: AFRA: A low cost high performance reliable routing for 3D mesh NoCs (SA, AS, MF, RB), pp. 332–337.
DATE-2012-PattiAAOCJJM #energy #middleware #network #performance: Middleware services for network interoperability in smart energy efficient buildings (EP, AA, FA, AO, AC, MJ, MJ, EM), pp. 338–339.
DATE-2012-TurturiciSFF #embedded #power management #realtime: Low-power embedded system for real-time correction of fish-eye automotive cameras (MT, SS, LF, EF), pp. 340–341.
DATE-2012-DonnoFSPB #energy #performance: Mechatronic system for energy efficiency in bus transport (MD, AF, AS, PP, AB), pp. 342–343.
DATE-2012-FaruqueC #automation #collaboration #embedded: Intelligent and collaborative embedded computing in automation engineering (MAAF, AC), pp. 344–345.
DATE-2012-XuLHRHT #analysis #power management: Variation-aware leakage power model extraction for system-level hierarchical power analysis (YX, BL, RH, BR, CH, JT), pp. 346–351.
DATE-2012-WangTLG #runtime: Runtime power estimator calibration for high-performance microprocessors (HW, SXDT, XL, AG), pp. 352–357.
DATE-2012-DrumlSWGH #estimation #manycore #smarttech: Estimation based power and supply voltage management for future RF-powered multi-core smart cards (ND, CS, RW, AG, JH), pp. 358–363.
DATE-2012-MahmoodPLM #clustering #energy #memory management #optimisation: Application-specific memory partitioning for joint energy and lifetime optimization (HM, MP, ML, EM), pp. 364–369.
DATE-2012-BozgaDHHLLT #analysis #embedded #modelling #state of the art #tool support: State-of-the-art tools and techniques for quantitative modeling and analysis of embedded systems (MB, AD, AH, HH, KGL, AL, JT), pp. 370–375.
DATE-2012-StattelmannGCBR #hybrid #modelling #simulation #using: Hybrid source-level simulation of data caches using abstract cache models (SS, GG, CC, OB, WR), pp. 376–381.
DATE-2012-WangH #compilation #embedded #optimisation #simulation: Accurate source-level simulation of embedded software with respect to compiler optimizations (ZW, JH), pp. 382–387.
DATE-2012-SheHMC #architecture #energy #scheduling: Scheduling for register file energy minimization in explicit datapath architectures (DS, YH, BM, HC), pp. 388–393.
DATE-2012-CordesM #algorithm #parallel #search-based #using: Multi-objective aware extraction of task-level parallelism using genetic algorithms (DC, PM), pp. 394–399.
DATE-2012-ChangCM #analysis: RTL analysis and modifications for improving at-speed test (KHC, HZC, ILM), pp. 400–405.
DATE-2012-KarimiCGP #fault #generative #testing: Test generation for clock-domain crossing faults in integrated circuits (NK, KC, PG, SP), pp. 406–411.
DATE-2012-SabenaRS #algorithm #testing: A new SBST algorithm for testing the register file of VLIW processors (DS, MSR, LS), pp. 412–417.
DATE-2012-JiangSCBP #algorithm #constraints #generative #memory management #on the: On the optimality of K longest path generation algorithm under memory constraints (JJ, MS, AC, BB, IP), pp. 418–423.
DATE-2012-ChakrabortyLBFCPKLA #challenge #embedded: Embedded systems and software challenges in electric vehicles (SC, ML, CB, SAF, NC, SP, YK, PL, HA), pp. 424–429.
DATE-2012-Al-HashimiM #framework #hardware #platform #question #verification: Accelerators and emulators: Can they become the platform of choice for hardware verification? (BMAH, RM), p. 430.
DATE-2012-ShoaibMGM #monitoring: A closed-loop system for artifact mitigation in ambulatory electrocardiogram monitoring (MS, GM, HG, SM), pp. 431–436.
DATE-2012-ShoaibJV #using: Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals (MS, NKJ, NV), pp. 437–442.
DATE-2012-YangCJTZ #multi #protocol #smarttech: A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare system (GY, JC, FJ, HT, LRZ), pp. 443–448.
DATE-2012-TanLXTC #branch #energy #predict #stack: Energy-efficient branch prediction with Compiler-guided History Stack (MT, XL, ZX, DT, XC), pp. 449–454.
DATE-2012-Sadooghi-AlvandiAM #branch #predict #towards: Toward virtualizing branch direction prediction (MSA, KA, AM), pp. 455–460.
DATE-2012-DangWTLYW #energy #named #performance: S/DC: A storage and energy efficient data prefetcher (XD, XW, DT, JL, JY, KW), pp. 461–466.
DATE-2012-KamalASP #approach #architecture #process: An architecture-level approach for mitigating the impact of process variations on extensible processors (MK, AAK, SS, MP), pp. 467–472.
DATE-2012-AisoposMIIN #named #probability: PCASA: Probabilistic control-adjusted Selective Allocation for shared caches (KA, JM, RI, RI, DN), pp. 473–478.
DATE-2012-DasSHMC #multi: Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores (AD, MS, NH, GM, ANC), pp. 479–484.
DATE-2012-HameedBH #adaptation #architecture #manycore #runtime: Dynamic cache management in multi-core architectures through run-time adaptation (FH, LB, JH), pp. 485–490.
DATE-2012-AbellanPABBMB #clustering #communication #design #framework: Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs (JLA, JFP, MEA, DB, DB, AM, LB), pp. 491–496.
DATE-2012-MarinhoNPP #analysis #float #scheduling: Preemption delay analysis for floating non-preemptive region scheduling (JM, VN, SMP, IP), pp. 497–502.
DATE-2012-FanQ #framework #manycore #platform #realtime #scheduling: Harmonic semi-partitioned scheduling for fixed-priority real-time tasks on multi-core platform (MF, GQ), pp. 503–508.
DATE-2012-HuangBRBK #scheduling #smt: Static scheduling of a Time-Triggered Network-on-Chip based on SMT solving (JH, JOB, AR, CB, AK), pp. 509–514.
DATE-2012-QuintonHE #analysis #formal method #realtime: Formal analysis of sporadic overload in real-time systems (SQ, MH, RE), pp. 515–520.
DATE-2012-CaiHMM #analysis #fault #memory management #metric: Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis (YC, EFH, OM, KM), pp. 521–526.
DATE-2012-ZhaCL #fault #memory management #modelling #testing: Modeling and testing of interference faults in the nano NAND Flash memory (JZ, XC, CLL), pp. 527–531.
DATE-2012-AzevedoVBDGTPAM #architecture #fault: Impact of resistive-open defects on the heat current of TAS-MRAM architectures (JA, AV, AB, LD, PG, ATS, GP, JAH, KM), pp. 532–537.
DATE-2012-JafariJL #analysis #scheduling #worst-case: Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling (FJ, AJ, ZL), pp. 538–541.
DATE-2012-DimitrakopoulosK #metaprogramming #multi #network: Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches (GD, EK), pp. 542–545.
DATE-2012-WangJZD #design #power management: Low power aging-aware register file design by duty cycle balancing (SW, TJ, CZ, GD), pp. 546–549.
DATE-2012-VyagrheswaruduDR #framework #interactive #named #optimisation #platform: PowerAdviser: An RTL power platform for interactive sequential optimizations (NV, SD, AR), pp. 550–553.
DATE-2012-CanedoF #cyber-physical #execution #industrial #parallel #towards: Towards parallel execution of IEC 61131 industrial cyber-physical systems applications (AC, MAAF), pp. 554–557.
DATE-2012-ChandrasekarMSH #debugging #design #industrial: A scan pattern debugger for partial scan industrial designs (KC, SKM, SS, MSH), pp. 558–561.
DATE-2012-BombieriFG #fault #framework #functional #named #simulation #verification: FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs (NB, FF, VG), pp. 562–565.
DATE-2012-PomataMTRL #design #performance: Exploiting binary translation for fast ASIP design space exploration on FPGAs (SP, PM, GT, LR, ML), pp. 566–569.
DATE-2012-WalravensD #architecture #design #energy: Design of a low-energy data processing architecture for WSN nodes (CW, WD), pp. 570–573.
DATE-2012-TabkhiS #approach #power management: Application-specific power-efficient approach for reducing register file vulnerability (HT, GS), pp. 574–577.
DATE-2012-GuerraF #online #scheduling: On-line scheduling of target sensitive periodic tasks with the gravitational task model (RG, GF), pp. 578–581.
DATE-2012-ChenMM #configuration management #manycore #online #scheduling: Online scheduling for multi-core shared reconfigurable fabric (LC, TM, TM), pp. 582–585.
DATE-2012-MohammadiEEM #fault #injection #named: SCFIT: A FPGA-based fault injection technique for SEU fault model (AM, ME, AE, SGM), pp. 586–589.
DATE-2012-Pyl #perspective #research: Research and innovation on Advanced Computing — an EU perspective (TVdP), p. 591.
DATE-2012-TetzlaffB #design: Memristor technology in future electronic system design (RT, AB), p. 592.
DATE-2012-SharifiAR #named #predict: TempoMP: Integrated prediction and management of temperature in heterogeneous MPSoCs (SS, RZA, TSR), pp. 593–598.
DATE-2012-SabrySA #3d #using: Thermal balancing of liquid-cooled 3D-MPSoCs using channel modulation (MMS, AS, DA), pp. 599–604.
DATE-2012-JuanCMC #modelling #optimisation #power management #statistics: Statistical thermal modeling and optimization considering leakage power variations (DCJ, YLC, DM, YWC), pp. 605–610.
DATE-2012-MengC #3d #analysis #energy #performance #runtime: Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiency (JM, AKC), pp. 611–616.
DATE-2012-HaedickeGD #metric #verification: A guiding coverage metric for formal verification (FH, DG, RD), pp. 617–622.
DATE-2012-MarinMLB #design #incremental #using #verification: Verification of partial designs using incremental QBF solving (PM, CM, MDTL, BB), pp. 623–628.
DATE-2012-LeMKV #debugging #satisfiability #using: Non-solution implications using reverse domination in a modern SAT-based debugging environment (BL, HM, BK, AGV), pp. 629–634.
DATE-2012-ThieleE #analysis #data flow #graph #optimisation #performance: Optimizing performance analysis for synchronous dataflow graphs with shared resources (DT, RE), pp. 635–640.
DATE-2012-LiuPC #composition #design #synthesis: Compositional system-level design exploration with planning of high-level synthesis (HYL, MP, LPC), pp. 641–646.
DATE-2012-SinhaRSB #component #design #multi: Correct-by-construction multi-component SoC design (RS, PSR, ZS, SB), pp. 647–652.
DATE-2012-TheelenKW #data flow #model checking: Model checking of Scenario-Aware Dataflow with CADP (BDT, JPK, HW), pp. 653–658.
DATE-2012-PrakashP #architecture #memory management #precise: An instruction scratchpad memory allocation for the precision timed architecture (AP, HDP), pp. 659–664.
DATE-2012-ShahRK #bound #scheduling #using: Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs (HS, AR, AK), pp. 665–670.
DATE-2012-GerdesKURS #realtime: Time analysable synchronisation techniques for parallelised hard real-time applications (MG, FK, TU, CR, PS), pp. 671–676.
DATE-2012-NicolaidisAZZKBTLTRKKDA #design #reliability: Design for test and reliability in ultimate CMOS (MN, LA, NEZ, YZ, TK, KAB, JT, SLL, CT, AR, MMK, JK, VD, DA), pp. 677–682.
DATE-2012-KnoedlerSLJHKSBZ #energy: Optimal energy management and recovery for FEV (KK, JS, SL, SJ, AH, EK, DS, OB, JZ), pp. 683–684.
DATE-2012-LeupersMPHSKV #platform: Virtual platforms: Breaking new grounds (RL, GM, RP, AH, FS, TK, MV), pp. 685–690.
DATE-2012-ParkKSNI #classification: An FPGA-based accelerator for cortical object classification (MSP, SK, JS, VN, MJI), pp. 691–696.
DATE-2012-ShafiqueZRKH #adaptation #power management: Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding (MS, BZ, SR, FK, JH), pp. 697–702.
DATE-2012-TtofisT #adaptation #algorithm #hardware #implementation #realtime #towards: Towards accurate hardware stereo correspondence: A real-time FPGA implementation of a segmentation-based adaptive support weight algorithm (CT, TT), pp. 703–708.
DATE-2012-ChatziparaskevasBP #difference #finite #parallel #using: An FPGA-based parallel processor for Black-Scholes option pricing using finite differences schemes (GC, AB, IP), pp. 709–714.
DATE-2012-SekaninaV #optimisation #polymorphism #satisfiability: A SAT-based fitness function for evolutionary optimization of polymorphic circuits (LS, ZV), pp. 715–720.
DATE-2012-KotiyalTR #design: Mach-Zehnder interferometer based design of all optical reversible binary adder (SK, HT, NR), pp. 721–726.
DATE-2012-PatilJCLYPLCC #logic: Weighted area technique for electromechanically enabled logic computation with cantilever-based NEMS switches (SP, MWJ, CLC, DL, ZY, WEP, DJL, SAC, TC), pp. 727–732.
DATE-2012-WangKAAW #design #energy #optimisation: Response-surface-based design space exploration and optimisation of wireless sensor nodes with tunable energy harvesters (LW, TJK, BMAH, MA, JW), pp. 733–738.
DATE-2012-LevequePLACSMC #embedded #feedback #modelling #multi: Holistic modeling of embedded systems with multi-discipline feedback: Application to a Precollision Mitigation Braking System (AL, FP, MML, HA, FC, SS, AM, LC), pp. 739–744.
DATE-2012-MaricauJG #analysis #learning #multi #reliability #using: Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection (EM, DdJ, GGEG), pp. 745–750.
DATE-2012-LiuMG #estimation #performance #problem: A fast analog circuit yield estimation method for medium and high dimensional problems (BL, JM, GGEG), pp. 751–756.
DATE-2012-MeissnerMLH #framework #graph #morphism #performance #synthesis #testing: Fast isomorphism testing for a graph-based analog circuit synthesis framework (MM, OM, LL, LH), pp. 757–762.
DATE-2012-Gamatie #design #streaming #using: Design of streaming applications on MPSoCs using abstract clocks (AG), pp. 763–768.
DATE-2012-FradetGP #data flow #named #parametricity: SPDF: A schedulable parametric data-flow MoC (PF, AG, PP), pp. 769–774.
DATE-2012-DamavandpeymaSBGC #data flow #graph #modelling: Modeling static-order schedules in synchronous dataflow graphs (MD, SS, TB, MG, HC), pp. 775–780.
DATE-2012-PiscitelliP #analysis #design #hybrid: Design space pruning through hybrid analysis in system-level design space exploration (RP, ADP), pp. 781–786.
DATE-2012-RichterC #delivery #manycore #reduction: Test pin count reduction for NoC-based Test delivery in multicore SOCs (MR, KC), pp. 787–792.
DATE-2012-JiangXE #3d #effectiveness #on the: On effective TSV repair for 3D-stacked ICs (LJ, QX, BE), pp. 793–798.
DATE-2012-HaronH #fault: DfT schemes for resistive open defects in RRAMs (NZH, SH), pp. 799–804.
DATE-2012-Peraldi-FratiBKK #modelling: Timing Modeling with AUTOSAR — Current state and future directions (MAPF, HB, DK, SK), pp. 805–809.
DATE-2012-QuintonEBY #analysis #challenge #probability #roadmap: Challenges and new trends in probabilistic timing analysis (SQ, RE, DB, PMY), pp. 810–815.
DATE-2012-ChenJM: QBf-based boolean function bi-decomposition (HC, MJ, JMS), pp. 816–819.
DATE-2012-EllenEO #automation #development #embedded #process #safety: Automatic transition between structural system views in a safety relevant embedded systems development process (CE, CE, MO), pp. 820–823.
DATE-2012-SekaninaS #image #logic #multi #towards: Towards new applications of multi-function logic: Image multi-filtering (LS, VS), pp. 824–827.
DATE-2012-GoossensKAG #realtime: Memory-map selection for firm real-time SDRAM controllers (SG, TK, BA, KG), pp. 828–831.
DATE-2012-LiangCZRZJC #3d #implementation #locality #optimisation #performance #realtime: Real-time implementation and performance optimization of 3D sound localization on GPUs (YL, ZC, SZ, KR, YZ, DLJ, DC), pp. 832–835.
DATE-2012-XhakoniBG #3d #image #performance: Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors (AX, DSSB, GGEG), pp. 836–839.
DATE-2012-DoustiP #latency #quantum: Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric (MJD, MP), pp. 840–843.
DATE-2012-ZhangPM #3d #analysis #grid #power management: Voltage propagation method for 3-D power grid analysis (CZ, VFP, GDM), pp. 844–847.
DATE-2012-NazinMR #optimisation: Yield optimization for radio frequency receiver at system level (SAN, DM, AR), pp. 848–851.
DATE-2012-LiuTW #analysis #approach #graph #parallel #statistics: Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach (XL, SXDT, HW), pp. 852–857.
DATE-2012-RudolfTWW #automation #configuration management #identification: Automated critical device identification for configurable analogue transistors (RR, PT, RW, PRW), pp. 858–861.
DATE-2012-ZimmermannBR #analysis #multi #power management: Analysis of multi-domain scenarios for optimized dynamic power management strategies (JZ, OB, WR), pp. 862–865.
DATE-2012-DasKSV #design #encryption #testing: PUF-based secure test wrapper design for cryptographic SoC testing (AD, ÜK, ARS, IV), pp. 866–869.
DATE-2012-AbeleinLHS #challenge #complexity #quality #robust: Complexity, quality and robustness — the challenges of tomorrow’s automotive electronics (UA, HL, DH, SS), pp. 870–871.
DATE-2012-NirmaierBTHKRLP #robust: Measuring and improving the robustness of automotive smart power microelectronics (TN, VMzB, MT, MH, MK, MR, JL, GP), pp. 872–873.
DATE-2012-LiRP #embedded #hardware #named: Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors (TL, RGR, SP), pp. 875–880.
DATE-2012-ZambelliIFCPOB #approach #trade-off: A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories (CZ, MI, MF, SDC, PP, PO, DB), pp. 881–886.
DATE-2012-KakoeeLB #architecture #clustering #communication #latency: A resilient architecture for low latency communication in shared-L1 processor clusters (MRK, IL, LB), pp. 887–892.
DATE-2012-OzTKT #analysis #parallel #thread #trade-off: Performance-reliability tradeoff analysis for multithreaded applications (IO, HRT, MTK, OT), pp. 893–898.
DATE-2012-LvKE #multi #performance #reduction #verification: Efficient Gröbner basis reductions for formal verification of galois field multipliers (JL, PK, FE), pp. 899–904.
DATE-2012-RayB #scalability #verification: Scalable progress verification in credit-based flow-control systems (SR, RKB), pp. 905–910.
DATE-2012-MitraBD #formal method #mining #ranking: Formal methods for ranking counterexamples through assumption mining (SM, AB, PD), pp. 911–916.
DATE-2012-TangZBM #analysis #correlation #modelling #statistics: Transistor-level gate model based statistical timing analysis considering correlations (QT, AZ, MB, NvdM), pp. 917–922.
DATE-2012-KnothJS #analysis #modelling: Current source modeling for power and timing analysis at different supply voltages (CK, HJ, US), pp. 923–928.
DATE-2012-YeYZX #scheduling: Clock skew scheduling for timing speculation (RY, FY, HZ, QX), pp. 929–934.
DATE-2012-GanPGM #design #distributed #flexibility #realtime #robust: Robust and flexible mapping for real-time distributed applications during the early design phases (JG, PP, FG, JM), pp. 935–940.
DATE-2012-BamakhramaZNS #automation #design #embedded #realtime #streaming: A methodology for automated design of hard-real-time embedded streaming systems (MB, JTZ, HN, TS), pp. 941–946.
DATE-2012-JiangEP #co-evolution #communication #constraints #design #distributed #embedded #realtime #security: Co-design techniques for distributed real-time embedded systems with communication security constraints (KJ, PE, ZP), pp. 947–952.
DATE-2012-RajendranPSK #analysis #encryption #fault #logic #perspective: Logic encryption: A fault analysis perspective (JR, YP, OS, RK), pp. 953–958.
DATE-2012-VeljkovicRV #generative #implementation #low cost #on the fly #random #testing: Low-cost implementations of on-the-fly tests for random number generators (FV, VR, IV), pp. 959–964.
DATE-2012-JinMM #encryption #evaluation #trust: Post-deployment trust evaluation in wireless cryptographic ICs (YJ, DM, YM), pp. 965–970.
DATE-2012-BrandlGWLGBFFRSSTCP: Batteries and battery management systems for electric vehicles (MB, HG, MW, VL, MG, FB, GF, LF, RR, RS, SS, AT, MC, WP), pp. 971–976.
DATE-2012-BoseBDGHJNRSVW #challenge #manycore #power management: Power management of multi-core chips: Challenges and pitfalls (PB, AB, JAD, MSG, MBH, HMJ, IN, JAR, JS, AV, AJW), pp. 977–982.
DATE-2012-BeniniFFM #composition #ecosystem #embedded #named #scalability: P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator (LB, EF, DF, DM), pp. 983–987.
DATE-2012-DoganCRBA #architecture #design #health #manycore #monitoring #power management #smarttech: Multi-core architecture design for ultra-low-power wearable health monitoring systems (AYD, JC, MR, AB, DA), pp. 988–993.
DATE-2012-HankendiC #energy #parallel #performance: Reducing the energy cost of computing through efficient co-scheduling of parallel workloads (CH, AKC), pp. 994–999.
DATE-2012-BeaumontHN #architecture #execution #hardware #replication #security #using: SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardware (MRB, BDH, TN), pp. 1000–1005.
DATE-2012-GuoSHGHNS #implementation: ASIC implementations of five SHA-3 finalists (XG, MS, SH, DG, MBH, LN, PS), pp. 1006–1011.
DATE-2012-ZohnerKSH #analysis: Side channel analysis of the SHA-3 finalists (MZ, MK, MS, SAH), pp. 1012–1017.
DATE-2012-CongHLZZ #replication #source code #streaming: Combining module selection and replication for throughput-driven streaming programs (JC, MH, BL, PZ, YZ), pp. 1018–1023.
DATE-2012-KondratyevLMW #synthesis #trade-off: Exploiting area/delay tradeoffs in high-level synthesis (AK, LL, MM, YW), pp. 1024–1029.
DATE-2012-ZuluagaBT #case study #design #predict #trade-off: Predicting best design trade-offs: A case study in processor customization (MZ, EVB, NPT), pp. 1030–1035.
DATE-2012-WilleDOO #automation #design #power management #synthesis #using: Automatic design of low-power encoders using reversible circuit synthesis (RW, RD, CO, AGO), pp. 1036–1041.
DATE-2012-SharmaCAHCD #power management #variability: Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM (VS, SC, MA, JH, FC, WD), pp. 1042–1047.
DATE-2012-PourshaghaghiFG: Sliding-Mode Control to Compensate PVT Variations in dual core systems (HRP, HF, JPdG), pp. 1048–1053.
DATE-2012-JeongKKRS #memory management #named #power management: MAPG: Memory access power gating (KJ, ABK, SK, TSR, RDS), pp. 1054–1059.
DATE-2012-XieLWPSC #energy #health #hybrid: State of health aware charge management in hybrid electrical energy storage systems (QX, XL, YW, MP, DS, NC), pp. 1060–1065.
DATE-2012-TodorovMRS #approximate #automation #memory management #transaction: Automated construction of a cycle-approximate transaction level model of a memory controller (VT, DMG, HR, US), pp. 1066–1071.
DATE-2012-EbeidFQS #design #embedded #modelling #refinement #uml: Refinement of UML/MARTE models for the design of networked embedded systems (ESME, FF, DQ, FS), pp. 1072–1077.
DATE-2012-WilleSD #consistency #debugging #modelling #ocl #uml: Debugging of inconsistent UML/OCL models (RW, MS, RD), pp. 1078–1083.
DATE-2012-NasseryO: An analytical technique for characterization of transceiver IQ imbalances in the loop-back mode (AN, SO), pp. 1084–1089.
DATE-2012-AbdallahSMA #testing: Testing RF circuits with true non-intrusive built-in sensors (LA, HGDS, SM, JA), pp. 1090–1095.
DATE-2012-WanK #embedded #monitoring: Monitoring active filters under automotive aging scenarios with embedded instrument (JW, HGK), pp. 1096–1101.
DATE-2012-RahimiBG #analysis: Analysis of instruction-level vulnerability to dynamic voltage and temperature variations (AR, LB, RKG), pp. 1102–1105.
DATE-2012-PellegriniSCFHJAAB #evaluation: CrashTest’ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions (AP, RS, LC, XF, SKSH, JJ, SVA, TMA, VB), pp. 1106–1109.
DATE-2012-SabryAC #approach #embedded #fault #hybrid: A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems (MMS, DA, FC), pp. 1110–1113.
DATE-2012-AxerSE #bound #probability: Probabilistic response time bound for CAN messages with arbitrary deadlines (PA, MS, RE), pp. 1114–1117.
DATE-2012-FanKGSH #design #integration: Exploring pausible clocking based GALS design for 40-nm system integration (XF, MK, EG, BS, CH), pp. 1118–1121.
DATE-2012-Chaturvedi #static analysis: Static analysis of asynchronous clock domain crossings (SC), pp. 1122–1125.
DATE-2012-SuriBE #approach #multi #problem #scalability: A scalable GPU-based approach to accelerate the multiple-choice knapsack problem (BS, UDB, PE), pp. 1126–1129.
DATE-2012-Mancini #kernel #memory management #synthesis: Enhancing non-linear kernels by an optimized memory hierarchy in a High Level Synthesis flow (SM, FR), pp. 1130–1133.
DATE-2012-SinkarWK #manycore #optimisation #performance: Workload-aware voltage regulator optimization for power efficient multi-core processors (AAS, HW, NSK), pp. 1134–1137.
DATE-2012-WeisLBW #3d #energy #performance: An energy efficient DRAM subsystem for 3D integrated SoCs (CW, IL, LB, NW), pp. 1138–1141.
DATE-2012-SoekenWD #invariant #modelling #ocl #uml: Eliminating invariants in UML/OCL models (MS, RW, RD), pp. 1142–1145.
DATE-2012-KimA #interface: On-chip source synchronous interface timing test scheme with calibration (HK, JAA), pp. 1146–1149.
DATE-2012-Graeb #challenge: ITRS 2011 Analog EDA Challenges and Approaches (HG), pp. 1150–1155.
DATE-2012-MorchePMV #architecture #named #power management: UWB: Innovative architectures enable disruptive low power wireless applications (DM, MP, GM, PV), pp. 1156–1160.
DATE-2012-FettweisNL: Pathways to servers of the future (GF, WEN, WL), pp. 1161–1166.
DATE-2012-PerinTBM #analysis #implementation: Amplitude demodulation-based EM analysis of different RSA implementations (GP, LT, PB, PM), pp. 1167–1172.
DATE-2012-NassarSGD #named #performance: RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs (MN, YS, SG, JLD), pp. 1173–1178.
DATE-2012-HeuserSS #modelling: Revealing side-channel issues of complex circuits by enhanced leakage models (AH, WS, MS), pp. 1179–1184.
DATE-2012-ChenSZX #3d #named #physics #synthesis: 3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs (YC, GS, QZ, YX), pp. 1185–1190.
DATE-2012-HansenS #multi #pipes and filters #resource management: Multi-token resource sharing for pipelined asynchronous systems (JH, MS), pp. 1191–1196.
DATE-2012-AksoyCFM #design #finite: Design of low-complexity digital finite impulse response filters on FPGAs (LA, EC, PFF, JCM), pp. 1197–1202.
DATE-2012-MahmoodSD #framework #linear #modelling #multi #performance: An efficient framework for passive compact dynamical modeling of multiport linear systems (ZM, RS, LD), pp. 1203–1208.
DATE-2012-NeogyR #analysis #design #injection: Analysis and design of sub-harmonically injection locked oscillators (AN, JSR), pp. 1209–1214.
DATE-2012-GaoXCG #design: Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping (PG, XX, JC, GGEG), pp. 1215–1220.
DATE-2012-SchoenmakerMSBTJ #scalability #simulation: Large signal simulation of integrated inductors on semi-conducting substrates (WS, MM, BDS, SB, CT, RJ), pp. 1221–1226.
DATE-2012-GoswamiLSC #implementation: Time-triggered implementations of mixed-criticality automotive software (DG, ML, RS, SC), pp. 1227–1232.
DATE-2012-MasrurGCCAB #analysis #communication #cyber-physical #hybrid #protocol: Timing analysis of cyber-physical applications for hybrid communication protocols (AM, DG, SC, JJC, AA, AB), pp. 1233–1238.
DATE-2012-LuoCH #approach #fault #synthesis: A cyberphysical synthesis approach for error recovery in digital microfluidic biochips (YL, KC, TYH), pp. 1239–1244.
DATE-2012-MuradoreQF #network #predict: Predictive control of networked control systems over differentiated services lossy networks (RM, DQ, PF), pp. 1245–1250.
DATE-2012-Voyiatzis #concurrent #logic #monitoring #multi: Input vector monitoring on line concurrent BIST based on multilevel decoding logic (IV), pp. 1251–1256.
DATE-2012-DuVM #latency #performance #reliability: High performance reliable variable latency carry select addition (KD, PJV, KM), pp. 1257–1262.
DATE-2012-HsuingCG: Salvaging chips with caches beyond repair (HH, BC, SKG), pp. 1263–1268.
DATE-2012-WuLMC #approach #correlation: Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms (KCW, MCL, DM, SCC), pp. 1269–1274.
DATE-2012-CamposanoGGJ: Moore meets maxwell (RC, DG, SGT, VJ), pp. 1275–1276.
DATE-2012-Marinissen #2d #3d #challenge #testing: Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs (EJM), pp. 1277–1282.
DATE-2012-StefanMAG #multi #performance: A TDM NoC supporting QoS, multicast, and fast connection set-up (RAS, AMM, JAA, KG), pp. 1283–1288.
DATE-2012-LiuJL #constant #parallel: Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC (SL, AJ, ZL), pp. 1289–1294.
DATE-2012-QianTT #configuration management #self #using: A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels (ZQ, YFT, CYT), pp. 1295–1300.
DATE-2012-BiZLCP #design: Spintronic memristor based temperature sensor design with CMOS current reference (XB, CZ, HL, YC, REP), pp. 1301–1306.
DATE-2012-WangBSD #3d #memory management #named: 3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory (YW, LADB, ZS, NDD), pp. 1307–1312.
DATE-2012-ZhangWLJC #design #symmetry: Asymmetry of MTJ switching and its implication to STT-RAM designs (YZ, XW, YL, AKJ, YC), pp. 1313–1318.
DATE-2012-SchrijenL #analysis #comparative: Comparative analysis of SRAM memories used as PUF primitives (GJS, VvdL), pp. 1319–1324.
DATE-2012-CherkaouiFAF #comparison #self: Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs (AC, VF, AA, LF), pp. 1325–1330.
DATE-2012-LiDT #authentication #detection #framework #hardware #self: A sensor-assisted self-authentication framework for hardware trojan detection (ML, AD, MT), pp. 1331–1336.
DATE-2012-AridhiZT #order #reduction #simulation #towards #using: Towards improving simulation of analog circuits using model order reduction (HA, MHZ, ST), pp. 1337–1342.
DATE-2012-VatajeluF #evaluation #parametricity #performance #reliability: Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation (EIV, JF), pp. 1343–1348.
DATE-2012-LiuTWY #simulation: A GPU-accelerated envelope-following method for switching power converter simulation (XL, SXDT, HW, HY), pp. 1349–1354.
DATE-2012-BrachtendorfBL #simulation: Simulation of the steady state of oscillators in the time domain (HGB, KB, RL), pp. 1355–1360.
DATE-2012-ChenLPCPWHWM #design: Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique (CC, WSL, RP, SC, JP, JW, RTH, HSPW, SM), pp. 1361–1366.
DATE-2012-HanPC #architecture #configuration management #power management: State-based full predication for low power coarse-grained reconfigurable architecture (KH, SP, KC), pp. 1367–1372.
DATE-2012-BonamyPPC #configuration management #named #power management: UPaRC — Ultra-fast power-aware reconfiguration controller (RB, HMP, SP, DC), pp. 1373–1378.
DATE-2012-MarianiSPZSB #architecture #configuration management #design #multi #resource management #runtime #using: Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures (GM, VMS, GP, VZ, CS, KB), pp. 1379–1384.
DATE-2012-Brenner: VLSI legalization with minimum perturbation by iterative augmentation (UB), pp. 1385–1390.
DATE-2012-LiuLC #optimisation: Agglomerative-based flip-flop merging with signal wirelength optimization (SYL, CJL, HMC), pp. 1391–1396.
DATE-2012-PonsMP #layout #metric: Fixed origin corner square inspection layout regularity metric (MP, MNM, CP), pp. 1397–1402.
DATE-2012-KesslerDTNRDBTP #aspect-oriented #manycore #performance #programmable: Programmability and performance portability aspects of heterogeneous multi-/manycore systems (CWK, UD, ST, RN, AR, UD, SB, JLT, SP), pp. 1403–1408.
DATE-2012-XuYCJW #3d #performance: Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC (YX, WY, QC, LJ, NW), pp. 1409–1412.
DATE-2012-NarayananDZT #design #using #verification: Verifying jitter in an analog and mixed signal design using dynamic time warping (RN, AD, MHZ, ST), pp. 1413–1416.
DATE-2012-MillerVG #automation #cyber-physical #mockup #named #testing #using: MEDS: Mockup Electronic Data Sheets for automated testing of cyber-physical systems using digital mockups (BM, FV, TG), pp. 1417–1420.
DATE-2012-HamoucheK #aspect-oriented #component #design #embedded #realtime: Component-based and aspect-oriented methodology and tool for Real-Time Embedded Control Systems Design (RH, RK), pp. 1421–1424.
DATE-2012-KirschPSCHHLLRSTV #cyber-physical #in the cloud #migration #problem: Cyber-physical cloud computing: The binding and migration problem (CMK, EP, RS, HC, RH, JH, FL, ML, AR, RS, RT, DV), pp. 1425–1428.
DATE-2012-BolchiniMS #adaptation #approach #architecture #fault #manycore #online: An adaptive approach for online fault management in many-core architectures (CB, AM, DS), pp. 1429–1432.
DATE-2012-CampagnaV #architecture #detection #fault #hybrid #validation: An hybrid architecture to detect transient faults in microprocessors: An experimental validation (SC, MV), pp. 1433–1438.
DATE-2012-FritzBAH #approach #evaluation #monitoring #performance: Evaluation of a new RFID system performance monitoring approach (GF, VB, OEKA, DH), pp. 1439–1442.
DATE-2012-PanagopoulosAR #approach #framework #hybrid #simulation: A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach (GP, CA, KR), pp. 1443–1446.
DATE-2012-LiuWWQS #embedded #memory management #process: A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems (DL, TW, YW, ZQ, ZS), pp. 1447–1450.
DATE-2012-ZhaoYZCL #architecture #array #memory management: Architecting a common-source-line array for bipolar non-volatile memory devices (BZ, JY, YZ, YC, HL), pp. 1451–1454.
DATE-2012-GuptaPMR #optimisation: Layout-aware optimization of stt mrams (SKG, SPP, NNM, KR), pp. 1455–1458.
DATE-2012-ChenCLSR: Characterization of the bistable ring PUF (QC, GC, PL, US, UR), pp. 1459–1462.
DATE-2012-WangLPW #algorithm #difference #linear #simulation: An operational matrix-based algorithm for simulating linear and fractional differential circuits (YW, HL, GKHP, NW), pp. 1463–1466.
DATE-2012-CupaiuoloI #flexibility #framework #implementation #performance #platform: A flexible and fast software implementation of the FFT on the BPE platform (TC, DLI), pp. 1467–1470.
DATE-2012-MittagKJR #constraints #design #geometry #physics: Hierarchical propagation of geometric constraints for full-custom physical design of ICs (MM, AK, GJ, WR), pp. 1471–1474.
DATE-2012-AbedW #online: Double-patterning friendly grid-based detailed routing with online conflict resolution (ISA, AGW), pp. 1475–1478.
DATE-2012-TsaiLL #analysis #configuration management #design: Design and analysis of via-configurable routing fabrics for structured ASICs (HPT, RBL, LCL), pp. 1479–1482.
DATE-2012-KroneAGF #smarttech #towards: Towards a wireless medical smart card (SK, BA, FG, GF), pp. 1483–1488.
DATE-2012-MandalKM #design #performance: A fast, source-synchronous ring-based network-on-chip design (AM, SPK, RNM), pp. 1489–1494.
DATE-2012-0002EGB #performance #using: Area efficient asynchronous SDM routers using 2-stage Clos switches (WS, DAE, JDG, WJB), pp. 1495–1500.
DATE-2012-ZhengLGBYC #communication #configuration management #power management: Power-efficient calibration and reconfiguration for on-chip optical communication (YZ, PL, MG, JB, SY, KTC), pp. 1501–1506.
DATE-2012-SunXX #design #memory management #modelling: Modeling and design exploration of FBDRAM as on-chip memory (GS, CX, YX), pp. 1507–1512.
DATE-2012-YunLY #ram: Bloom filter-based dynamic wear leveling for phase-change RAM (JY, SL, SY), pp. 1513–1518.
DATE-2012-WangLLZLSCY #architecture: A compression-based area-efficient recovery architecture for nonvolatile processors (YW, YL, YL, DZ, SL, BS, MFC, HY), pp. 1519–1524.
DATE-2012-CondoMM #architecture: A Network-on-Chip-based turbo/LDPC decoder architecture (CC, MM, GM), pp. 1525–1530.
DATE-2012-YuBL #adaptation #complexity #power management: A complexity adaptive channel estimator for low power (ZY, CHvB, HL), pp. 1531–1536.
DATE-2012-KwongG #architecture #constant #geometry #performance: A high performance split-radix FFT with constant geometry architecture (JK, MG), pp. 1537–1542.
DATE-2012-StojilovicNSBI #flexibility: Selective flexibility: Breaking the rigidity of datapath merging (MS, DN, LS, PB, PI), pp. 1543–1548.
DATE-2012-RosiereDDW #design: An out-of-order superscalar processor on FPGA: The ReOrder Buffer design (MR, JLD, ND, FW), pp. 1549–1554.
DATE-2012-GrudnitskyBH #architecture #configuration management: Partial online-synthesis for mixed-grained reconfigurable architectures (AG, LB, JH), pp. 1555–1560.
DATE-2012-ChaoCTHC #configuration management #scheduling: Congestion-aware scheduling for NoC-based reconfigurable systems (HLC, YRC, SYT, PAH, SJC), pp. 1561–1566.
DATE-2012-TangHCH #generative #logic #multi #reduction: Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction (KFT, PKH, CNC, CYH), pp. 1567–1572.
DATE-2012-YangLTW #modelling: Almost every wire is removable: A modeling and solution for removing any circuit wire (XY, TKL, WCT, YLW), pp. 1573–1578.
DATE-2012-RayMEBJC: Mapping into LUT structures (SR, AM, NE, RKB, SJ, CC), pp. 1579–1584.
DATE-2012-Sasao #generative: Row-shift decompositions for index generation functions (TS), pp. 1585–1590.
DATE-2012-LiDX #process: Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations (ML, AD, LX), pp. 1591–1596.
DATE-2012-HsuCCLC #effectiveness #on the #pseudo: On effective flip-chip routing via pseudo single redistribution layer (HWH, MLC, HMC, HCL, SHC), pp. 1597–1602.
DATE-2012-HamoudaAK #automation #image #modelling #novel: AIR (Aerial Image Retargeting): A novel technique for in-fab automatic model-based retargeting-for-yield (AYH, MA, KSK), pp. 1603–1608.
DATE-2012-BesteT #analysis #robust #standard: Layout-Driven Robustness Analysis for misaligned Carbon Nanotubes in CNTFET-based standard cells (MB, MBT), pp. 1609–1614.
DATE-2012-JongheMGMTS #modelling #roadmap #testing #verification: Advances in variation-aware modeling, verification, and testing of analog ICs (DdJ, EM, GGEG, TM, BT, HGDS), pp. 1615–1620.

Wolfgang Rosenstiel, Lothar ThieleProceedings of the 16th Conference and Exhibition on Design, Automation and Test in EuropeDATE, 2012.

Contents (307 items)

Wolfgang Rosenstiel, Lothar Thiele
Proceedings of the 16th Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2012.