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Travelled to:
2 × USA
Collaborated with:
P.Subramaniam F.Chang C.Visweswariah R.Chadha C.Lo H.N.Nham
Talks about:
level (2) generat (1) develop (1) circuit (1) second (1) effici (1) calcul (1) analog (1) verif (1) simul (1)

Person: Chin-Fu Chen

DBLP DBLP: Chen:Chin=Fu

Contributed to:

DAC 19881988
DAC 19841984

Wrote 3 papers:

DAC-1988-ChangCS #performance
An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits (FCC, CFC, PS), pp. 282–287.
DAC-1988-VisweswariahCC #development #verification
Model Development and Verification for High Level Analog Blocks (CV, RC, CFC), pp. 376–382.
DAC-1984-ChenLNS #generative
The second generation motis mixed-mode simulator (CFC, CYL, HNN, PS), pp. 10–17.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.