Travelled to:7 × USA
Collaborated with:J.A.Wehbeh R.A.Rohrer P.N.Strenski K.Kalafala X.Bai R.Chadha C.Chen K.Ravindran S.G.Walker S.Narayan J.A.G.Jess S.R.Naidu R.H.J.M.Otten A.R.Conn I.M.Elfadel W.W.Molzen P.R.O'Brien C.B.Whan R.Goldman K.Keutzer C.Bittlestone A.Bootehsaz S.Y.Borkar E.Chen L.Scheffer
Talks about:statist (4) circuit (4) time (4) digit (3) increment (2) simul (2) optim (2) block (2) base (2) uncertainti (1)
Person: Chandramouli Visweswariah
DBLP: Visweswariah:Chandramouli
Contributed to:
2004200320021999199319911988Wrote 8 papers:
- DAC-2004-GoldmanKBBBCSV #question #statistics
- Is statistical timing statistically significant? (RG, KK, CB, AB, SYB, EC, LS, CV), p. 498.
- DAC-2004-VisweswariahRKWN #analysis #first-order #incremental #statistics
- First-order incremental block-based statistical timing analysis (CV, KR, KK, SGW, SN), pp. 331–336.
- DAC-2003-JessKNOV #parametricity #predict #statistics
- Statistical timing for parametric yield prediction of digital integrated circuits (JAGJ, KK, SRN, RHJMO, CV), pp. 932–937.
- DAC-2002-BaiVS #optimisation
- Uncertainty-aware circuit optimization (XB, CV, PNS), pp. 58–63.
- DAC-1999-ConnEMOSVW #optimisation #using
- Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation (ARC, IME, WWM, PRO, PNS, CV, CBW), pp. 452–459.
- DAC-1993-VisweswariahW #incremental #simulation
- Incremental Event-Driven Simulation of Digital FET Circuits (CV, JAW), pp. 737–741.
- DAC-1991-VisweswariahR #performance #simulation
- Efficient Simulation of Bipolar Digital ICs (CV, RAR), pp. 32–37.
- DAC-1988-VisweswariahCC #development #verification
- Model Development and Verification for High Level Analog Blocks (CV, RC, CFC), pp. 376–382.