Travelled to:
1 × Canada
9 × USA
Collaborated with:
H.N.Nham D.Dutt S.Nahar R.Varadarajan C.R.Bonapace ∅ H.Shin A.K.Bose A.Singhal R.M.Arlein J.Matousek W.L.Steiger C.Ong J.Li K.Chiang C.Chen P.Subramaniam S.Yao C.Cheng P.Kozak E.Pacas-Skewes K.W.Wu
Talks about:
algorithm (4) compact (4) generat (3) vlsi (3) cell (3) circuit (2) automat (2) symbol (2) layout (2) effici (2)
Person: Chi-Yuan Lo
DBLP: Lo:Chi=Yuan
Contributed to:
Wrote 13 papers:
- DAC-1993-YaoCDNL #using
- Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP (SZY, CKC, DD, SN, CYL), pp. 395–400.
- SIGMOD-1993-SinghalAL #design #named #object-oriented
- DDB: An Object Oriented Design Data Manager for VLSI CAD (AS, RMA, CYL), pp. 467–470.
- STOC-1992-LoMS
- Ham-Sandwich Cuts in R^d (CYL, JM, WLS), pp. 539–545.
- DAC-1991-DuttL #assembly #constraints #generative #on the
- On Minimal Closure Constraint Generation for Symbolic Cell Assembly (DD, CYL), pp. 736–739.
- DAC-1990-LoV #algorithm
- An O(n1.5logn) 1-d Compaction Algorithm (CYL, RV), pp. 382–387.
- DAC-1989-BonapaceL #algorithm #design
- An O(nlogm) Algorithm for VLSI Design Rule Checking (CRB, CYL), pp. 503–507.
- DAC-1989-Lo #automation #generative #layout
- Automatic Tub Region Generation for Symbolic Layout Compaction (CYL), pp. 302–306.
- DAC-1989-OngLL #automation #named #synthesis
- GENAC: An Automatic Cell Synthesis Tool (CLO, JTL, CYL), pp. 239–244.
- DAC-1989-ShinL #2d #algorithm #layout #performance
- An Efficient Two-Dimensional Layout Compaction Algorithm (HS, CYL), pp. 290–295.
- DAC-1988-ChiangNL #algorithm #analysis #performance
- Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2 (KWC, SN, CYL), pp. 471–475.
- DAC-1984-ChenLNS #generative
- The second generation motis mixed-mode simulator (CFC, CYL, HNN, PS), pp. 10–17.
- DAC-1983-LoNB #data type
- A data structure for MOS circuits (CYL, HNN, AKB), pp. 619–624.
- DAC-1982-BoseKLNPW #fault
- A fault simulator for MOS LSI circuits (AKB, PK, CYL, HNN, EPS, KWW), pp. 400–409.