Travelled to:1 × Germany
1 × USA
Collaborated with:C.Chen P.Subramaniam L.Ye P.Feldmann R.Chadha N.Ns F.Cano
Talks about:level (2) submicron (1) parasit (1) circuit (1) effici (1) effect (1) design (1) calcul (1) verif (1) digit (1)
Person: Foong-Charn Chang
DBLP: Chang:Foong=Charn
Contributed to:
1999
1988Wrote 2 papers:
- DATE-1999-YeCFCNC #design #verification
- Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs (LY, FCC, PF, RC, NN, FC), pp. 658–663.
- DAC-1988-ChangCS #performance
- An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits (FCC, CFC, PS), pp. 282–287.