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Travelled to:
1 × Estonia
3 × USA
Collaborated with:
C.Wu B.Wu C.Wu T.Lin H.Yeh C.Lai C.Chou Y.Ho C.Hsieh K.Tang P.Huang
Talks about:
interpol (3) base (3) constraint (2) framework (2) synthesi (2) design (2) verif (2) model (2) check (2) sat (2)

Person: Chung-Yang (Ric) Huang

DBLP DBLP: Huang:Chung=Yang_(Ric)

Contributed to:

DAC 20132013
DAC 20122012
TACAS 20122012
DAC 20112011

Wrote 6 papers:

DAC-2013-WuH #constraints #framework #multi #random #robust #set #theorem proving #verification
A robust constraint solving framework for multiple constraint sets in constrained random verification (BHW, CY(H), p. 7.
DAC-2013-WuWLH #algorithm #generative #model checking #satisfiability
A counterexample-guided interpolant generation algorithm for SAT-based model checking (CYW, CAW, CYL, CY(H), p. 6.
DAC-2012-ChouHHH #design #model checking
Symbolic model checking on SystemC designs (CNC, YSH, CH, CY(H), pp. 327–333.
TACAS-2012-YehWH #design #framework #named #open source #synthesis #towards #verification
QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification (HHY, CYW, CY(H), pp. 377–391.
DAC-2011-LinH #satisfiability #using
Using SAT-based Craig interpolation to enlarge clock gating functions (THL, CY(H), pp. 621–626.
DAC-2011-TangWHH #incremental #logic #multi #synthesis
Interpolation-based incremental ECO synthesis for multi-error logic rectification (KFT, CAW, PKH, CY(H), pp. 146–151.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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