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Travelled to:
2 × France
2 × USA
Collaborated with:
C.(.Huang C.Huang C.Wu C.Lai K.Tang P.Huang Y.Yeh H.Lin T.Lin C.Lee
Talks about:
base (3) sat (3) interpol (2) circuit (2) check (2) counterexampl (1) increment (1) algorithm (1) synthesi (1) synchron (1)

Person: Chi-An Wu


Contributed to:

DAC 20132013
DAC 20112011
DATE 20112011
DATE 20072007

Wrote 4 papers:

DAC-2013-WuWLH #algorithm #generative #model checking #satisfiability
A counterexample-guided interpolant generation algorithm for SAT-based model checking (CYW, CAW, CYL, CY(H), p. 6.
DAC-2011-TangWHH #incremental #logic #multi #synthesis
Interpolation-based incremental ECO synthesis for multi-error logic rectification (KFT, CAW, PKH, CY(H), pp. 146–151.
DATE-2011-YehHWL #framework #simulation
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method (YFY, CYH, CAW, HCL), pp. 353–358.
DATE-2007-WuLLH #named #robust #satisfiability
QuteSAT: a robust circuit-based SAT solver for complex circuit structure (CAW, THL, CCL, CYH), pp. 1313–1318.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.