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Travelled to:
1 × France
Collaborated with:
S.Bailey J.Bhasker J.Lewis P.J.Ashenden
Talks about:
product (1) improv (1) design (1) verif (1) vhdl (1)

Person: Erich Marschner

DBLP DBLP: Marschner:Erich

Contributed to:

DATE DF 20042004

Wrote 1 papers:

DATE-DF-2004-BaileyMBLA #design #verification
Improving Design and Verification Productivity with VHDL-200x (SB, EM, JB, JL, PJA), pp. 332–335.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.