Travelled to:1 × Germany
1 × USA
2 × France
Collaborated with:T.Drane P.Y.K.Cheung W.Luk D.B.Thomas S.T.Fleming D.R.Ghica J.Wickerson M.Batty T.S.0001 K.Shi D.Boland E.A.Stott S.Bayliss
Talks about:datapath (2) arithmet (2) wordlength (1) overclock (1) transpar (1) synthesi (1) accuraci (1) synthes (1) softwar (1) product (1)
Person: George A. Constantinides
DBLP: Constantinides:George_A=
Contributed to:
2015
201420112001
2017Wrote 5 papers:
- DATE-2015-ThomasFCG #hardware
- Transparent linking of compiled software and synthesized hardware (DBT, STF, GAC, DRG), pp. 1084–1089.
- DAC-2014-ShiBSBC #online #synthesis #trade-off
- Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs (KS, DB, EAS, SB, GAC), p. 6.
- DATE-2011-DraneC #optimisation
- Optimisation of mutually exclusive arithmetic sum-of-products (TD, GAC), pp. 1388–1393.
- DATE-2001-ConstantinidesCL #heuristic #multi
- Heuristic datapath allocation for multiple wordlength systems (GAC, PYKC, WL), pp. 791–797.
- POPL-2017-WickersonBSC #automation #consistency #memory management #modelling
- Automatically comparing memory consistency models (JW, MB, TS0, GAC), pp. 190–204.