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Travelled to:
2 × Germany
Collaborated with:
M.Pflanz S.Müller M.Schölzel C.Rousselle A.Behling T.Mohaupt U.Krautz C.Jacobi H.Tast K.Weber
Talks about:
error (3) fault (2) transient (1) processor (1) transfer (1) multicor (1) hierarch (1) coverag (1) toward (1) system (1)

Person: Heinrich Theodor Vierhaus

DBLP DBLP: Vierhaus:Heinrich_Theodor

Contributed to:

PDP 20132013
DATE 20062006
DATE 20012001

Wrote 3 papers:

PDP-2013-MullerSV #fault #multi #towards
Towards a Graceful Degradable Multicore-System by Hierarchical Handling of Hard Errors (SM, MS, HTV), pp. 302–309.
DATE-2006-KrautzP0TWV #detection #fault #formal method #logic #using
Evaluating coverage of error detection logic for soft errors using formal methods (UK, MP, CJ, HWT, KW, HTV), pp. 176–181.
DATE-2001-RoussellePBMV #embedded #fault
A register-transfer-level fault simulator for permanent and transient faults in embedded processors (CR, MP, AB, TM, HTV), p. 811.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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