BibSLEIGH — Proceedings of the 10th Conference on Design, Automation and Test in Europe

Georges G. E. Gielen
Proceedings of the 10th Conference on Design, Automation and Test in Europe
DATE, 2006.

SYS

@proceedings{DATE-2006,
	address       = "Munich, Germany",
	editor        = "Georges G. E. Gielen",
	publisher     = "{European Design and Automation Association, Leuven, Belgium}",
	title         = "{Proceedings of the 10th Conference on Design, Automation and Test in Europe}",
	volume        = "3-9810801-0-6",
	year          = 2006,
}

Contents (267 items)

DATE-2006-Vries #challenge #convergence: EDA challenges in the converging application world (RPdV), p. 1.
DATE-2006-Rhines #design: Sociology of design and EDA (WCR), p. 2.
DATE-2006-RuggieroGBPM #framework #multi #scheduling: Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip (MR, AG, DB, FP, MM), pp. 3–8.
DATE-2006-GuzWBCGK #capacity #design #performance: Efficient link capacity and QoS design for network-on-chip (ZG, IW, EB, IC, RG, AK), pp. 9–14.
DATE-2006-BertozziABP #migration #multi: Supporting task migration in multi-processor systems-on-chip: a feasibility study (SB, AA, DB, AP), pp. 15–20.
DATE-2006-ZengFSCZC #domain model #order #reduction: Time domain model order reduction by wavelet collocation method (XZ, LF, YS, WC, DZ, CC), pp. 21–26.
DATE-2006-ZhouSMS #analysis #composition #grid #power management #scalability #using: Large power grid analysis using domain decomposition (QZ, KS, KM, DCS), pp. 27–32.
DATE-2006-BalachandranBCWRNB #analysis #grid #modelling #power management: Analysis and modeling of power grid transmission lines (JB, SB, GC, TW, WDR, BN, EB), pp. 33–38.
DATE-2006-WangM #algorithm #analysis #multi: A logarithmic full-chip thermal analysis algorithm based on multi-layer Green’s function (BW, PM), pp. 39–44.
DATE-2006-TanjiWKA #analysis #scalability #using: Large scale RLC circuit analysis using RLCG-MNA formulation (YT, TW, HK, HA), pp. 45–46.
DATE-2006-GillPW #analysis #fault #logic: Soft delay error analysis in logic circuits (BSG, CAP, FGW), pp. 47–52.
DATE-2006-TsengLC #2d #using: A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap (TWT, JFL, DMC), pp. 53–58.
DATE-2006-RossiSM #analysis: Analysis of the impact of bus implemented EDCs on on-chip SSN (DR, CS, CM), pp. 59–64.
DATE-2006-KranitisMLTPGH #embedded #fault #pipes and filters #testing: Optimal periodic testing of intermittent faults in embedded pipelined processor applications (NK, AM, NL, GT, AMP, DG, CH), pp. 65–70.
DATE-2006-AlmukhaizimM #concurrent #detection #fault: Berger code-based concurrent error detection in asynchronous burst-mode machines (SA, YM), pp. 71–72.
DATE-2006-CarbognaniBFKF #power management: Two-phase resonant clocking for ultra-low-power hearing aid applications (FC, FB, NF, HK, WF), pp. 73–78.
DATE-2006-LeeKKCY #adaptation #using: A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes (SJL, KK, HK, NC, HJY), pp. 79–80.
DATE-2006-NiclassSC #array: A single photon avalanche diode array fabricated in deep-submicron CMOS technology (CN, MS, EC), pp. 81–86.
DATE-2006-Friedman #design #matlab: MATLAB/Simulink for automotive systems design (JF), pp. 87–88.
DATE-2006-ConradD #development #modelling: Model-based development of in-vehicle software (MC, HD), pp. 89–90.
DATE-2006-Lamberg #modelling #testing: Model-based testing of automotive electronics (KL), p. 91.
DATE-2006-Heighton #design: Designing signal processing systems for FPGAs (JH), p. 92.
DATE-2006-VanderperrenD #matlab #uml: From UML/SysML to Matlab/Simulink: current state and future perspectives (YV, WD), p. 93.
DATE-2006-ViaudPG #modelling #parallel #performance #simulation: An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles (EV, FP, AG), pp. 94–99.
DATE-2006-BeltrameSSLP #simulation: Exploiting TLM and object introspection for system-level simulation (GB, DS, CS, DL, CP), pp. 100–105.
DATE-2006-HabibiTSLM #performance #using #verification: Efficient assertion based verification using TLM (AH, ST, AS, DL, OAM), pp. 106–111.
DATE-2006-DErricoQ #approach: Constructing portable compiled instruction-set simulators: an ADL-driven approach (JD, WQ), pp. 112–117.
DATE-2006-MuraliCRGM #multi #network: A methodology for mapping multiple use-cases onto networks on chips (SM, MC, AR, KG, GDM), pp. 118–123.
DATE-2006-AngioliniMCBR #layout: Contrasting a NoC and a traditional interconnect fabric with layout awareness (FA, PM, SC, LB, LR), pp. 124–129.
DATE-2006-SrinivasanC #architecture #complexity #design #heuristic: A low complexity heuristic for design of custom network-on-chip architectures (KS, KSC), pp. 130–135.
DATE-2006-PionteckAK #configuration management: A dynamically reconfigurable packet-switched network-on-chip (TP, CA, RK), pp. 136–137.
DATE-2006-MajidzadehS #design #higher-order #novel: Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs (VM, OS), pp. 138–143.
DATE-2006-YavariSR #design #hybrid: Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation (MY, OS, ÁRV), pp. 144–149.
DATE-2006-VandersteenBDR: Systematic stability-analysis method for analog circuits (GV, SB, PD, YR), pp. 150–155.
DATE-2006-ZhangZD #modelling #named #parametricity #process: ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits (HZ, YZ, AD), pp. 156–161.
DATE-2006-GianniniNBCCDB #design #power management #synthesis: A synthesis tool for power-efficient base-band filter design (VG, PN, FDB, JC, BC, SD, AB), pp. 162–163.
DATE-2006-RaoCBS #algorithm #fault #performance: An efficient static algorithm for computing the soft error rates of combinational circuits (RRR, KC, DB, DS), pp. 164–169.
DATE-2006-OmanaCRM #detection #fault #low cost #reliability: Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects (MO, JMC, DR, CM), pp. 170–175.
DATE-2006-KrautzP0TWV #detection #fault #formal method #logic #using: Evaluating coverage of error detection logic for soft errors using formal methods (UK, MP, CJ, HWT, KW, HTV), pp. 176–181.
DATE-2006-IgnatNSN #classification #impact analysis #operating system #realtime: Soft-error classification and impact analysis on real-time operating systems (NI, BN, YS, GN), pp. 182–187.
DATE-2006-Shrikumar #protocol: 40Gbps de-layered silicon protocol engine for TCP record (HS), pp. 188–193.
DATE-2006-LucasHRERWGFHES #configuration management #framework #platform #realtime: A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications (AdCL, SH, PR, RE, HR, GW, KG, RF, WH, SE, GS), pp. 194–199.
DATE-2006-BrackKW #design: Disclosing the LDPC code decoder design space (TB, FK, NW), pp. 200–205.
DATE-2006-DimondML #automation #memory management #resource management: Automating processor customisation: optimised memory access and resource sharing (RGD, OM, WL), pp. 206–211.
DATE-2006-BiswasDIP #architecture #automation #functional #identification: Automatic identification of application-specific functional units with architecturally visible storage (PB, NDD, PI, LP), pp. 212–217.
DATE-2006-GrossschadlIPTV #algorithm #case study #design #encryption #set: Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography (JG, PI, LP, ST, AKV), pp. 218–223.
DATE-2006-ZmilyK #embedded #energy #performance: Simultaneously improving code size, performance, and energy in embedded processors (AZ, CK), pp. 224–229.
DATE-2006-SchirnerD #analysis #modelling #transaction: Quantitative analysis of transaction level models for the AMBA bus (GS, RD), pp. 230–235.
DATE-2006-KunzliPBT #analysis #formal method #performance #simulation: Combining simulation and formal methods for system-level performance analysis (SK, FP, LB, LT), pp. 236–241.
DATE-2006-ViehlSBR #analysis #design #modelling #performance #simulation #uml: Formal performance analysis and simulation of UML/SysML models for ESL design (AV, TS, OB, WR), pp. 242–247.
DATE-2006-WildHO #architecture #evaluation #performance #simulation #transaction #using: Performance evaluation for system-on-chip architectures using trace-based transaction level simulation (TW, AH, RO), pp. 248–253.
DATE-2006-MarculescuRS #design #idea #network #question: Is “Network” the next “Big Idea” in design? (RM, JMR, ALSV), pp. 254–256.
DATE-2006-FrehseKR #abstraction #refinement #using #verification: Verifying analog oscillator circuits using forward/backward abstraction refinement (GF, BHK, RAR), pp. 257–262.
DATE-2006-MeiR #analysis #performance #using: Efficient AC analysis of oscillators using least-squares methods (TM, JSR), pp. 263–268.
DATE-2006-McConaghyG #canonical #modelling #performance: Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns (TM, GGEG), pp. 269–274.
DATE-2006-MartensE #synthesis #top-down: Top-down heterogeneous synthesis of analog and mixed-signal systems (EM, GGEG), pp. 275–280.
DATE-2006-MartinezLC #order #reduction #using: Nonlinear model order reduction using remainder functions (JAM, SPL, DMC), pp. 281–282.
DATE-2006-YangV #analysis #evaluation #performance #synthesis: Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis (HY, RV), pp. 283–284.
DATE-2006-SehgalGMC #design #framework: Hierarchy-aware and area-efficient test infrastructure design for core-based system chips (AS, SKG, EJM, KC), pp. 285–290.
DATE-2006-HePE #clustering #scheduling #testing: Power constrained and defect-probability driven SoC test scheduling with test set partitioning (ZH, ZP, PE), pp. 291–296.
DATE-2006-YonedaMF #multi #scheduling: Power-constrained test scheduling for multi-clock domain SoCs (TY, KM, HF), pp. 297–302.
DATE-2006-LiuLP #scheduling: Reuse-based test access and integrated test scheduling for network-on-chip (CL, ZL, DKP), pp. 303–308.
DATE-2006-Kundu #analysis #design: A design for failure analysis (DFFA) technique to ensure incorruptible signatures (SK), pp. 309–310.
DATE-2006-GuptaJL #automaton #generative #quantum #testing: Test generation for combinational quantum cellular automata (QCA) circuits (PG, NKJ, LL), pp. 311–316.
DATE-2006-AbdollahiP #analysis #diagrams #quantum #synthesis #using: Analysis and synthesis of quantum circuits by using quantum decision diagrams (AA, MP), pp. 317–322.
DATE-2006-SuHC #synthesis: Droplet routing in the synthesis of digital microfluidic biochips (FS, WLH, KC), pp. 323–328.
DATE-2006-RickettsIVI #scheduling: Priority scheduling in digital microfluidics-based biochips (AJR, KMI, NV, MJI), pp. 329–334.
DATE-2006-BhaduriSCTGG #analysis #architecture #design #fault tolerance #framework #hybrid: A hybrid framework for design and analysis of fault-tolerant architectures (DB, SKS, DC, VET, PSG, MG), pp. 335–336.
DATE-2006-MinzTL #3d: Optical routing for 3D system-on-package (JRM, ST, SKL), pp. 337–338.
DATE-2006-RaghavanLJCV #architecture #distributed #multi #thread: Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors (PR, AL, MJ, FC, DV), pp. 339–344.
DATE-2006-MolnosHCE #composition #multi #performance: Compositional, efficient caches for a chip multi-processor (AMM, MJMH, SDC, JTJvE), pp. 345–350.
DATE-2006-EyermanEB #design #embedded #performance: Efficient design space exploration of high performance embedded out-of-order processors (SE, LE, KDB), pp. 351–356.
DATE-2006-VandierendonckML #configuration management: Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses (HV, PM, JDL), pp. 357–362.
DATE-2006-AhnYPKKC #algorithm #architecture #configuration management: A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures (MA, JWY, YP, YK, MK, KC), pp. 363–368.
DATE-2006-PanainteBV #compilation #configuration management: Compiler-driven FPGA-area allocation for reconfigurable computing (EMP, KB, SV), pp. 369–374.
DATE-2006-NascimentoL #architecture #clustering #complexity #configuration management #image: Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures (PSBdN, MEdL), pp. 375–380.
DATE-2006-YiNMKAL #configuration management #scheduling: System-level scheduling on instruction cell based reconfigurable systems (YY, IN, MM, SK, TA, IL), pp. 381–386.
DATE-2006-BuhlerKBHSSPR #design #process: DFM/DFY design for manufacturability and yield — influence of process variations in digital, analog and mixed-signal circuit design (MB, JK, JB, JH, US, RS, MP, AR), pp. 387–392.
DATE-2006-WeiTD #communication #configuration management #design #multi: Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems (YW, HT, AD), pp. 393–398.
DATE-2006-YavariSR06a: Double-sampling single-loop sigma-delta modulator topologies for broadband applications (MY, OS, ÁRV), pp. 399–404.
DATE-2006-MoezE #distributed #process: A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS process (KKM, MIE), pp. 405–409.
DATE-2006-GarciaMN: Bootstrapped full--swing CMOS driver for low supply voltage operation (JCG, JAMN, SN), pp. 410–411.
DATE-2006-BernardiSSSR #cost analysis #effectiveness: An effective technique for minimizing the cost of processor software-based diagnosis in SoCs (PB, ES, MS, GS, MSR), pp. 412–417.
DATE-2006-YangC #fault: Timing-reasoning-based delay fault diagnosis (KY, KTC), pp. 418–423.
DATE-2006-LinC #multi: Multiple-fault diagnosis based on single-fault activation and single-output observation (YCL, KTC), pp. 424–429.
DATE-2006-ZhouW #constraints #self: Software-based self-test of processors under power constraints (JZ, HJW), pp. 430–435.
DATE-2006-HuangG #fault: Diagnosis of defects on scan enable and clock trees (YH, KG), pp. 436–437.
DATE-2006-ChoRJ #embedded #realtime: Lock-free synchronization for dynamic embedded real-time systems (HC, BR, EDJ), pp. 438–443.
DATE-2006-WandelerMT #analysis #performance #realtime: Performance analysis of greedy shapers in real-time systems (EW, AM, LT), pp. 444–449.
DATE-2006-HeniaE #multi #using: Improved offset-analysis using multiple timing-references (RH, RE), pp. 450–455.
DATE-2006-LuZSLS #scheduling #set: Procrastinating voltage scheduling with discrete frequency sets (ZL, YZ, MRS, JL, KS), pp. 456–461.
DATE-2006-YangCBHS #communication #framework #integration: Communication and co-simulation infrastructure for heterogeneous system integration (GY, XC, FB, HH, ALSV), pp. 462–467.
DATE-2006-KempfKWALM #estimation #fine-grained #framework #performance #using: A SW performance estimation framework for early system-level-design using fine-grained instrumentation (TK, KK, SW, GA, RL, HM), pp. 468–473.
DATE-2006-ReyesKBAN #case study #design #modelling #simulation: A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study (VR, WK, TB, GA, AN), pp. 474–479.
DATE-2006-StreubuhrFHTDS #architecture #modelling #multi #performance #realtime: Task-accurate performance modeling in SystemC for real-time multi-processor architectures (MS, JF, CH, JT, RD, TS), pp. 480–481.
DATE-2006-PaulinPLBBLLL #distributed #modelling #multi #power management: Distributed object models for multi-processor SoC’s, with application to low-power multimedia wireless systems (PGP, CP, ML, EB, OB, DL, BL, DL), pp. 482–487.
DATE-2006-KogelB #embedded #multi #platform #prototype: Virtual prototyping of embedded platforms for wireless and multimedia (TK, MB), pp. 488–490.
DATE-2006-Benini #design: Application specific NoC design (LB), pp. 491–495.
DATE-2006-ViswanathAJ #automation #pipes and filters #power management: Automatic insertion of low power annotations in RTL for pipelined microprocessors (VV, JAA, WAHJ), pp. 496–501.
DATE-2006-MochockiLC #3d #analysis #mobile: Power analysis of mobile 3D graphics (BM, KL, SC), pp. 502–507.
DATE-2006-PettisRL #automation #operating system #policy #runtime: Automatic run-time selection of power policies for operating systems (NP, JR, YHL), pp. 508–513.
DATE-2006-XianL #adaptation #energy #multi #reduction: Energy reduction by workload adaptation in a multi-process environment (CX, YHL), pp. 514–519.
DATE-2006-ParkCR #adaptation #energy #image #quality #trade-off: Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off (JP, JHC, KR), pp. 520–521.
DATE-2006-LaMeresK #encoding #induction: Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission (BJL, SPK), pp. 522–527.
DATE-2006-ZhangHC #analysis #correlation #statistics: Statistical timing analysis with path reconvergence and spatial correlations (LZ, YH, CCPC), pp. 528–532.
DATE-2006-AbbaspourFP #analysis #statistics: Non-gaussian statistical interconnect timing analysis (SA, HF, MP), pp. 533–538.
DATE-2006-NazarianP #analysis: Cell delay analysis based on rate-of-current change (SN, MP), pp. 539–544.
DATE-2006-Liu: A practical method to estimate interconnect responses to variabilities (FL), pp. 545–546.
DATE-2006-SebekeJHFSG #challenge #reliability: Test and reliability challenges in automotive microelectronics (CS, CJ, KH, SF, JS, PG), p. 547.
DATE-2006-KanajanZPS #architecture #distributed #integration #trade-off #using: Exploring trade-off’s between centralized versus decentralized automotive architectures using a virtual integration environment (SK, HZ, CP, ALSV), pp. 548–553.
DATE-2006-Weber #communication #network: Management of complex automotive communication networks (TW), pp. 554–555.
DATE-2006-HerkersdorfS #architecture #flexibility #named: AutoVision: flexible processor architecture for video-assisted driving (AH, WS), p. 556.
DATE-2006-Muller-Glaser #design #modelling: Domain specific model driven design for automotive electronic control units (KDMG), p. 557.
DATE-2006-Degardins #architecture #assessment: Electric and electronic vehicle architecture assessment (PD), p. 558.
DATE-2006-Leteinturier #challenge: Automotive semi-conductor trend & challenges (PL), p. 559.
DATE-2006-UmKHKCKEK #design #modelling #platform: A systematic IP and bus subsystem modeling for platform-based system design (JU, WCK, SH, YTK, KMC, JTK, SKE, TK), pp. 560–564.
DATE-2006-PatelSB #behaviour #design: Heterogeneous behavioral hierarchy for system level designs (HDP, SKS, RAB), pp. 565–570.
DATE-2006-SchaumontSV #design #hardware #semantics: Design with race-free hardware semantics (PS, SKS, IV), pp. 571–576.
DATE-2006-ProchnowH #modelling: Comfortable modeling of complex reactive systems (SP, RvH), pp. 577–578.
DATE-2006-AhmedM #design #performance #uml #using: Faster exploration of high level design alternatives using UML for better partitions (WA, DM), pp. 579–580.
DATE-2006-LeupersKKP #configuration management #design #embedded #set #synthesis: A design flow for configurable embedded processors based on optimized instruction set extension synthesis (RL, KK, SK, MP), pp. 581–586.
DATE-2006-RobellySCF #architecture #design #energy #performance #programmable #trade-off: Energy efficiency vs. programmability trade-off: architectures and design principles (PR, HS, KCC, GF), pp. 587–592.
DATE-2006-BurgBWSB #algorithm: Advanced receiver algorithms for MIMO wireless communications (AB, MB, MW, CS, HB), pp. 593–598.
DATE-2006-Shaver #architecture #deployment #generative: Next generation architectures can dramatically reduce the 4G deployment cycle (DS), p. 599.
DATE-2006-ChattopadhyayGKWSILAM #automation #embedded: Automatic ADL-based operand isolation for embedded processors (AC, BG, DK, EMW, OS, HI, RL, GA, HM), pp. 600–605.
DATE-2006-MonchieroPSV #hardware #optimisation #performance: Power/performance hardware optimization for synchronization intensive applications in MPSoCs (MM, GP, CS, OV), pp. 606–611.
DATE-2006-KumarA #power management: An analytical state dependent leakage power model for FPGAs (AK, MA), pp. 612–617.
DATE-2006-MallikSBZ #design #optimisation #power management: Smart bit-width allocation for low power optimization in a systemc based ASIC design environment (AM, DS, PB, HZ), pp. 618–623.
DATE-2006-SundaresanM #energy #optimisation: Value-based bit ordering for energy optimization of on-chip global signal buses (KS, NRM), pp. 624–625.
DATE-2006-SridharanC #modelling #multi #using: Modeling multiple input switching of CMOS gates in DSM technology using HDMR (JS, TC), pp. 626–631.
DATE-2006-SoffkeZMG #analysis #approach #combinator #statistics: A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits (OS, PZ, TM, MG), pp. 632–637.
DATE-2006-Maurer #simulation #symmetry #using: Using conjugate symmetries to enhance gate-level simulations (PMM), pp. 638–643.
DATE-2006-Al-JunaidK #modelling #using: HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slope (HAJ, TJK), pp. 644–645.
DATE-2006-NegreirosCS #reduction: An improved RF loopback for test time reduction (MN, LC, AAS), pp. 646–651.
DATE-2006-LiuI #optimisation #scheduling #using: Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking (CL, VI), pp. 652–657.
DATE-2006-SrinivasanTC #automation #low cost #multi #online #platform: Online RF checkers for diagnosing multi-gigahertz automatic test boards on low cost ATE platforms (GS, FT, AC), pp. 658–663.
DATE-2006-DhayniMRB #functional #linear #pseudo: Pseudorandom functional BIST for linear and nonlinear MEMS (AD, SM, LR, AB), pp. 664–669.
DATE-2006-AbbasIA #detection: On-chip 8GHz non-periodic high-swing noise detector (MA, MI, KA), pp. 670–671.
DATE-2006-LahiriBCM #clustering #speech: Battery-aware code partitioning for a text to speech system (AL, AB, MC, SM), pp. 672–677.
DATE-2006-LiCY #adaptation #embedded #energy #optimisation #performance #realtime: Performance optimization for energy-aware adaptive checkpointing in embedded real-time systems (ZL, HC, SY), pp. 678–683.
DATE-2006-CorneaND #mobile #optimisation: Software annotations for power optimization on mobile devices (RC, AN, NDD), pp. 684–689.
DATE-2006-XueOLKK #architecture #clustering #embedded #memory management: Dynamic partitioning of processing and memory resources in embedded MPSoC architectures (LX, ÖÖ, FL, MTK, IK), pp. 690–695.
DATE-2006-KandemirCLIK #clustering #process: Activity clustering for leakage management in SPMs (MTK, GC, FL, MJI, IK), pp. 696–697.
DATE-2006-Stanley-MarbellLR #adaptation #concurrent #embedded #library #multi #thread: Adaptive data placement in an embedded multiprocessor thread library (PSM, KL, AR), pp. 698–699.
DATE-2006-PasrichaD #architecture #communication #memory management #named: COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC (SP, NDD), pp. 700–705.
DATE-2006-IzosimovPEP #distributed #embedded #fault tolerance #performance #synthesis #trade-off: Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems (VI, PP, PE, ZP), pp. 706–711.
DATE-2006-OgrasMLC #architecture #communication #optimisation: Communication architecture optimization: making the shortest path shorter in regular networks-on-chip (ÜYO, RM, HGL, NC), pp. 712–717.
DATE-2006-ManolacheEP #communication #optimisation #synthesis: Buffer space optimisation with communication synthesis and traffic shaping for NoCs (SM, PE, ZP), pp. 718–723.
DATE-2006-LinHF #hardware #interface: Cooptimization of interface hardware and software for I/O controllers (KJL, SHH, SCF), pp. 724–725.
DATE-2006-NollL #aspect-oriented: Cross disciplinary aspects (4G wireless special day) (TGN, UL), p. 726.
DATE-2006-LambretteH #industrial #mobile #named: SoC: fuelling the hopes of the mobile industry (UL, BAH), p. 727.
DATE-2006-SekarLRD #adaptation #configuration management #platform: Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms (KS, KL, AR, SD), pp. 728–733.
DATE-2006-DensmoreDS #analysis #architecture #performance: FPGA architecture characterization for system level performance analysis (DD, AD, ALSV), pp. 734–739.
DATE-2006-BartzasMPACST #data type #design #energy #network #refinement: Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications (AB, SM, GP, DA, FC, DS, AT), pp. 740–745.
DATE-2006-RadhakrishnanGP #multi: Customization of application specific heterogeneous multi-pipeline processors (SR, HG, SP), pp. 746–751.
DATE-2006-ThornbergO #memory management #realtime #specification #video: Impact of bit-width specification on the memory hierarchy for a real-time video processing system (BT, MO), pp. 752–753.
DATE-2006-GuillotBRCGA #diagrams #performance #using: Efficient factorization of DSP transforms using taylor expansion diagrams (JG, EB, QR, MJC, DGP, SA), pp. 754–755.
DATE-2006-VenkataramanHLS #optimisation: Integrated placement and skew optimization for rotary clocking (GV, JH, FL, CCNS), pp. 756–761.
DATE-2006-KimH: Associative skew clock routing for difficult instances (MSK, JH), pp. 762–767.
DATE-2006-DuttA #incremental #locality #performance #using: Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations (SD, HA), pp. 768–773.
DATE-2006-HuangML #fault: Defect tolerance of QCA tiles (JH, MM, FL), pp. 774–779.
DATE-2006-PaulKKAR #design #estimation #performance #reliability: Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits (BCP, KK, HK, MAA, KR), pp. 780–785.
DATE-2006-BhanjaOLP #design #novel #robust: Novel designs for thermally robust coplanar crossing in QCA (SB, MO, FL, SP), pp. 786–791.
DATE-2006-NepalBMPZ #design #fault #memory management: Designing MRF based error correcting circuits for memory elements (KN, RIB, JLM, WRP, AZ), pp. 792–793.
DATE-2006-SteinhammerGAK: A time-triggered ethernet (TTE) switch (KS, PG, AA, HK), pp. 794–799.
DATE-2006-Schoeberl #java #predict: A time predictable Java processor (MS), pp. 800–805.
DATE-2006-WehrmeisterPB #embedded #generative #java #object-oriented #optimisation #realtime #specification: Optimizing the generation of object-oriented real-time embedded applications based on the real-time specification for Java (MAW, CEP, LBB), pp. 806–811.
DATE-2006-GiunchigliaNT #quantifier: Quantifier structure in search based procedures for QBFs (EG, MN, AT), pp. 812–817.
DATE-2006-JinS #analysis #satisfiability: Strong conflict analysis for propositional satisfiability (HJ, FS), pp. 818–823.
DATE-2006-ShekharKE #equivalence #multi #verification: Equivalence verification of arithmetic datapaths with multiple word-length operands (NS, PK, FE), pp. 824–829.
DATE-2006-X #architecture #design #tool support: 4G applications, architectures, design methodology and tools for MPSoC, pp. 830–831.
DATE-2006-ChakrabortySDMMP #bound #optimisation: Thermal resilient bounded-skew clock tree optimization methodology (AC, PS, KD, AM, EM, MP), pp. 832–837.
DATE-2006-PaciMPB #design #power management: Exploring “temperature-aware” design in low-power MPSoCs (GP, PM, FP, LB), pp. 838–843.
DATE-2006-YangGZSD #adaptation #analysis #design #synthesis: Adaptive chip-package thermal analysis for synthesis and design (YY, Z(G, CZ, LS, RPD), pp. 844–849.
DATE-2006-WangXVI #analysis #optimisation: On-chip bus thermal analysis and optimization (FW, YX, NV, MJI), pp. 850–855.
DATE-2006-RaychowdhuryPBR #case study #comparative #power management: Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies (AR, BCP, SB, KR), pp. 856–861.
DATE-2006-BanerjeeRMB #fine-grained #logic #power management #synthesis #using: Low power synthesis of dynamic logic circuits using fine-grained clock gating (NB, KR, HMM, SB), pp. 862–867.
DATE-2006-BabighianBMM: Enabling fine-grain leakage management by voltage anchor insertion (PB, LB, AM, EM), pp. 868–873.
DATE-2006-MamagkakisAPCSM #automation #embedded #memory management: Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems (SM, DA, CP, FC, DS, JMM), pp. 874–875.
DATE-2006-AlimondaACP #approach #energy #optimisation #pipes and filters #runtime: A control theoretic approach to run-time energy optimization of pipelined processing in MPSoCs (AA, AA, SC, AP), pp. 876–877.
DATE-2006-WongL #3d: 3D floorplanning with thermal vias (EW, SKL), pp. 878–883.
DATE-2006-IizukaIA #layout #optimisation: Timing-driven cell layout de-compaction for yield optimization by critical area minimization (TI, MI, KA), pp. 884–889.
DATE-2006-KahngPSW #lens: Lens aberration aware timing-driven placement (ABK, CHP, PS, QW), pp. 890–895.
DATE-2006-KrusemanH #detection #fault #on the: On test conditions for the detection of open defects (BK, MH), pp. 896–901.
DATE-2006-RosselloS #fault #identification: A compact model to identify delay faults due to crosstalk (JLR, JS), pp. 902–906.
DATE-2006-PomeranzR #detection #fault #generative #testing: Generation of broadside transition fault test sets that detect four-way bridging faults (IP, SMR), pp. 907–912.
DATE-2006-NelsonZDBPMB #fault: Extraction of defect density and size distributions from wafer sort test results (JEN, TZ, RD, JGB, NP, WM, RD(B), pp. 913–918.
DATE-2006-ScharwachterHLAM #hardware #interprocedural #multi #network #optimisation #thread #using: An interprocedural code optimization technique for network processors using hardware multi-threading support (HS, MH, RL, GA, HM), pp. 919–924.
DATE-2006-UdayakumaranB: An integrated scratch-pad allocator for affine and non-affine code (SU, RB), pp. 925–930.
DATE-2006-ChenOKK #array #data access #memory management: Dynamic scratch-pad memory management for irregular array access patterns (GC, ÖÖ, MTK, MK), pp. 931–936.
DATE-2006-ShinKKH #embedded #memory management: Restructuring field layouts for embedded memory systems (KS, JK, SK, HH), pp. 937–942.
DATE-2006-HuangG06a #adaptation #compilation #embedded #power management #scalability: Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities (PKH, SG), pp. 943–944.
DATE-2006-ParkOPSH #embedded #source code: Dynamic code overlay of SDF-modeled programs on low-end embedded systems (HwP, KO, SP, MmS, SH), pp. 945–946.
DATE-2006-SethuramanV #architecture #automation #generative #multi #named #using: optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs (BS, RV), pp. 947–952.
DATE-2006-LiuBCLM #architecture #hardware #performance: Hardware efficient architectures for Eigenvalue computation (YL, CSB, PYKC, PHWL, SJM), pp. 953–958.
DATE-2006-KulkarniB #concurrent #framework #memory management #platform #thread: Memory centric thread synchronization on platform FPGAs (CK, GJB), pp. 959–964.
DATE-2006-QuSN #configuration management #parallel #runtime: A parallel configuration model for reducing the run-time reconfiguration overhead (YQ, JPS, JN), pp. 965–969.
DATE-2006-Havinga #network: Wireless sensor networks and beyond (PJMH), p. 970.
DATE-2006-El-HoiydiACCDEGGLMPPPRRRV #power management: The ultra low-power wiseNET system (AEH, CA, RC, SC, JDD, CCE, FG, SG, EL, TM, VP, FXP, PDP, NR, AR, DR, PV), pp. 971–976.
DATE-2006-Beutel #framework #platform #prototype #using: Fast-prototyping using the BTnode platform (JB), pp. 977–982.
DATE-2006-ChenMBR #case study #design #power management: Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design (QC, SM, AB, KR), pp. 983–988.
DATE-2006-SchusterNPF #architecture #power management: Architectural and technology influence on the optimal total power consumption (CS, JLN, CP, PAF), pp. 989–994.
DATE-2006-AmelifardFP #using: Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment (BA, FF, MP), pp. 995–1000.
DATE-2006-GandhiM #energy #multi #using: Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits (KRG, NRM), pp. 1001–1006.
DATE-2006-BombieriFP #evaluation #on the #reuse #verification: On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL (NB, FF, GP), pp. 1007–1012.
DATE-2006-BalarinP #functional #generative #interface #specification #verification: Functional verification methodology based on formal interface specification and transactor generation (FB, RP), pp. 1013–1018.
DATE-2006-Harris #metric #process #validation: A coverage metric for the validation of interacting processes (IGH), pp. 1019–1024.
DATE-2006-JerinicLHM #functional #metric #verification: New methods and coverage metrics for functional verification (VJ, JL, UH, DM), pp. 1025–1030.
DATE-2006-KruppM #classification #functional #random testing #testing: Classification trees for random tests and functional coverage (AK, WM), pp. 1031–1032.
DATE-2006-KavousianosKN #multi #performance #testing #using: Efficient test-data compression for IP cores using multilevel Huffman coding (XK, EK, DN), pp. 1033–1038.
DATE-2006-PolianF #constraints #functional #testing: Functional constraints vs. test compression in scan-based delay testing (IP, HF), pp. 1039–1044.
DATE-2006-ZengI #concurrent #testing #using: Concurrent core test for SOC using shared test set and scan chain disable (GZ, HI), pp. 1045–1050.
DATE-2006-WangBC #performance #using: Efficient unknown blocking using LFSR reseeding (SW, KJB, STC), pp. 1051–1052.
DATE-2006-ChaoWCWC #using: Coverage loss by using space compactors in presence of unknown values (MCTC, SW, STC, WW, KTC), pp. 1053–1054.
DATE-2006-ChengG #energy #online #realtime #scheduling: Online energy-aware I/O device scheduling for hard real-time systems (HC, SG), pp. 1055–1060.
DATE-2006-HsuCK #constraints #energy #multi #realtime #synthesis: Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint (HRH, JJC, TWK), pp. 1061–1066.
DATE-2006-CherrounDF #constraints #equation #scheduling #using: Scheduling under resource constraints using dis-equations (HC, AD, PF), pp. 1067–1072.
DATE-2006-MaC #embedded #energy #multi #platform #realtime #scalability #trade-off: Scalable performance-energy trade-off exploration of embedded real-time systems on multiprocessor platforms (ZM, FC), pp. 1073–1078.
DATE-2006-ChaiK #detection #symmetry: Building a better Boolean matcher and symmetry detector (DC, AK), pp. 1079–1084.
DATE-2006-SovianiTE #composition #optimisation: Optimizing sequential cycles through Shannon decomposition and retiming (CS, OT, SAE), pp. 1085–1090.
DATE-2006-Albrecht #incremental #latency #performance #scalability #scheduling: Efficient incremental clock latency scheduling for large circuits (CA), pp. 1091–1096.
DATE-2006-ReddyWM #architecture #nondeterminism: Analyzing timing uncertainty in mesh-based clock architectures (SMR, GRW, RM), pp. 1097–1102.
DATE-2006-BoniventoCS #design #industrial #network #platform: Platform-based design of wireless sensor networks for industrial applications (AB, LPC, ALSV), pp. 1103–1107.
DATE-2006-HandziskiKWW #network: An environment for controlled experiments with in-house sensor networks (VH, AK, AW, AW), p. 1108.
DATE-2006-BonnetLM #framework #monitoring #named #network #towards: Hogthrob: towards a sensor network infrastructure for sow monitoring (wireless sensor network special day) (PB, ML, KM), p. 1109.
DATE-2006-ChakrapaniACKPS #architecture #embedded #probability: Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology (LNC, BESA, SC, PK, KVP, BS), pp. 1110–1115.
DATE-2006-BudnikR #distributed #network #novel #power management #using: Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network (MMB, KR), pp. 1116–1121.
DATE-2006-Chang #design #power management: An ultra low-power TLB design (YJC), pp. 1122–1127.
DATE-2006-RongP #algorithm #formal method #markov #online #process: Determining the optimal timeout values for a power-managed system based on the theory of Markovian processes: offline and online algorithms (PR, MP), pp. 1128–1133.
DATE-2006-MatulaM #algorithm #float #formal method #generative #performance #standard #traversal #verification: A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division (DWM, LDM), pp. 1134–1138.
DATE-2006-FeySVD #on the #satisfiability: On the relation between simulation-based and SAT-based diagnosis (GF, SS, AGV, RD), pp. 1139–1144.
DATE-2006-AngioliniCLFFB #design #framework: An integrated open framework for heterogeneous MPSoC design space exploration (FA, JC, RL, FF, CF, LB), pp. 1145–1150.
DATE-2006-KimHG #execution #parallel #using: Parallel co-simulation using virtual synchronization with redundant host execution (DK, SH, RG), pp. 1151–1156.
DATE-2006-NakamuraST #integration #performance #simulation: An efficient and portable scheduler for RTOS simulation and its certified integration to SystemC (HN, NS, NT), pp. 1157–1158.
DATE-2006-DililloRAG #process #reduction: Minimizing test power in SRAM through reduction of pre-charge activity (LD, PMR, BMAH, PG), pp. 1159–1164.
DATE-2006-SutharD #detection #fault #multi #online #performance #testing: Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults (VS, SD), pp. 1165–1170.
DATE-2006-HosseinabadyBBN #concurrent #testing: A concurrent testing method for NoC switches (MH, AB, MNB, ZN), pp. 1171–1176.
DATE-2006-HelyBFR #design: A secure scan design methodology (DH, FB, MLF, BR), pp. 1177–1178.
DATE-2006-HeJ #configuration management #framework #named #synthesis: RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics (CH, MFJ), pp. 1179–1184.
DATE-2006-KastnerGHBKBS #communication #layout #optimisation #synthesis: Layout driven data communication optimization for high level synthesis (RK, WG, XH, FB, AK, PB, MS), pp. 1185–1190.
DATE-2006-MohantyVK #optimisation: Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits (SPM, RV, EK), pp. 1191–1196.
DATE-2006-ParkESNDP #automation #embedded #generative #performance: Automatic generation of operation tables for fast exploration of bypasses in embedded processors (SP, EE, AS, AN, ND, YP), pp. 1197–1202.
DATE-2006-PanditKMP #hardware #higher-order #synthesis: High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count (SP, SK, CAM, AP), pp. 1203–1204.
DATE-2006-WangYIG #embedded #image #verification: Disjunctive image computation for embedded software verification (CW, ZY, FI, AG), pp. 1205–1210.
DATE-2006-ShyamB #hybrid #verification: Distance-guided hybrid verification with GUIDO (SS, VB), pp. 1211–1216.
DATE-2006-DasBDC #design #model checking #question #what: What lies between design intent coverage and model checking? (SD, PB, PD, PPC), pp. 1217–1222.
DATE-2006-HassenT #on the #probability #term rewriting #verification: On the numerical verification of probabilistic rewriting systems (JBH, ST), pp. 1223–1224.
DATE-2006-FeyGD #verification: Avoiding false negatives in formal verification for protocol-driven blocks (GF, DG, RD), pp. 1225–1226.
DATE-2006-MaciiPFADZ #design #matter #power management #question #tool support: Low-power design tools: are EDA vendors taking this matter seriously? (EM, MP, DF, RCA, AD, RZ), p. 1227.
DATE-2006-KarlssonEP #design #petri net #representation #using #verification: Formal verification of systemc designs using a petri-net based representation (DK, PE, ZP), pp. 1228–1233.
DATE-2006-KaneMS #pipes and filters #verification: Monolithic verification of deep pipelines with collapsed flushing (RK, PM, SKS), pp. 1234–1239.
DATE-2006-KooM #functional #generative #pipes and filters #testing #using #validation: Functional test generation using property decompositions for validation of pipelined processors (HMK, PM), pp. 1240–1245.
DATE-2006-Morin-AlloryB #monitoring #specification: Proven correct monitors from PSL specifications (KMA, DB), pp. 1246–1251.
DATE-2006-Al-ArsHG #fault #modelling #testing: Space of DRAM fault models and corresponding testing (ZAA, SH, AJvdG), pp. 1252–1257.
DATE-2006-BensoBCNP #automation #fault #testing: Automatic march tests generations for static linked faults in SRAMs (AB, AB, SDC, GDN, PP), pp. 1258–1263.
DATE-2006-PomeranzR06a #fault: Test compaction for transition faults under transparent-scan (IP, SMR), pp. 1264–1269.
DATE-2006-WangCG #fault #formal method #probability #testing #using: Test set enrichment using a probabilistic fault model and the theory of output deviations (ZW, KC, MG), pp. 1270–1275.
DATE-2006-AsadiSTK #analysis: Vulnerability analysis of L2 cache elements to single event upsets (HA, VS, MBT, DRK), pp. 1276–1281.
DATE-2006-Kim #fault: Area-efficient error protection for caches (SK), pp. 1282–1287.
DATE-2006-HealyVEBLLL #architecture #performance #trade-off: Microarchitectural floorplanning under performance and thermal tradeoff (MBH, MV, ME, CSB, SKL, HHSL, GHL), pp. 1288–1293.
DATE-2006-HosangadiFK #optimisation #using: Optimizing high speed arithmetic circuits using three-term extraction (AH, FF, RK), pp. 1294–1299.
DATE-2006-BernasconiCDV #network #performance: Efficient minimization of fully testable 2-SPP networks (AB, VC, RD, TV), pp. 1300–1305.
DATE-2006-Ruiz-SautuaMMH #multi #optimisation #performance: Pre-synthesis optimization of multiplications to improve circuit performance (RRS, MCM, JMM, RH), pp. 1306–1311.
DATE-2006-LiuH #logic #synthesis: Crosstalk-aware domino logic synthesis (YYL, TH), pp. 1312–1317.
DATE-2006-KlingaufGG #architecture #named #transaction: TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC (WK, HG, RG), pp. 1318–1323.
DATE-2006-ArpinenKSHH #configuration management #distributed #execution #framework #multi #platform #uml: Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications (TA, PK, ES, MH, TDH), pp. 1324–1329.
DATE-2006-MullerBJ #design #multi: ASIP-based multiprocessor SoC design for simple and double binary turbo decoding (OM, AB, MJ), pp. 1330–1335.

Georges G. E. GielenProceedings of the 10th Conference on Design, Automation and Test in EuropeDATE, 2006.

Contents (267 items)

Georges G. E. Gielen
Proceedings of the 10th Conference on Design, Automation and Test in Europe
DATE, 2006.