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Travelled to:
1 × Germany
2 × Canada
2 × France
2 × United Kingdom
4 × USA
Collaborated with:
F.Somenzi H.Kim H.Han K.Ravi M.Awedh A.Kuehlmann C.Wang G.D.Hachtel P.Spacek J.Pierce R.P.Kurshan
Talks about:
satisfi (7) analysi (5) solver (3) circus (3) conflict (2) circuit (2) boolean (2) hybrid (2) effici (2) assign (2)

Person: HoonSang Jin

DBLP DBLP: Jin:HoonSang

Contributed to:

DATE 20112011
SAT 20092009
CAV 20082008
DATE 20062006
DAC 20052005
TACAS 20052005
CAV 20042004
DAC 20042004
SAT 20042004
SAT 20042005
TACAS 20022002
SMT 20062007

Wrote 14 papers:

DATE-2011-HanJS #analysis
Clause simplification through dominator analysis (HH, HJ, FS), pp. 143–148.
SAT-2009-KimSJ #modulo theories #performance #satisfiability
Efficient Term-ITE Conversion for Satisfiability Modulo Theories (HK, FS, HJ), pp. 195–208.
CAV-2008-KimJRSPKS #analysis #random #simulation
Application of Formal Word-Level Analysis to Constrained Random Simulation (HK, HJ, KR, PS, JP, RPK, FS), pp. 487–490.
DATE-2006-JinS #analysis #satisfiability
Strong conflict analysis for propositional satisfiability (HJ, FS), pp. 818–823.
DAC-2005-JinS #performance
Prime clauses for fast enumeration of satisfying assignments to boolean circuits (HJ, FS), pp. 750–753.
TACAS-2005-JinHS #analysis #performance
Efficient Conflict Analysis for Finding All Satisfying Assignments of a Boolean Circuit (HJ, HH, FS), pp. 287–300.
CAV-2004-JinAS #bound #model checking #named #satisfiability #towards
CirCUs: A Satisfiability Solver Geared towards Bounded Model Checking (HJ, MA, FS), pp. 519–522.
DAC-2004-WangJHS #bound #model checking #satisfiability
Refining the SAT decision ordering for bounded model checking (CW, HJ, GDH, FS), pp. 535–538.
SAT-2004-JinS #hybrid #named #satisfiability
CirCUs: A Hybrid Satisfiability Solver (HJ, FS), pp. 47–55.
SAT-J-2004-JinS05 #hybrid #named #satisfiability
CirCUs: A Hybrid Satisfiability Solver (HJ, FS), pp. 211–223.
TACAS-2002-JinKS #analysis #reachability #scheduling
Fine-Grain Conjunction Scheduling for Symbolic Reachability Analysis (HJ, AK, FS), pp. 312–326.
TACAS-2002-JinRS #fault
Fate and Free Will in Error Traces (HJ, KR, FS), pp. 445–459.
SMT-J-2006-KimJS #difference #finite #integer #logic
Disequality Management in Integer Difference Logic via Finite Instantiations (HK, HJ, FS), pp. 47–66.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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