BibSLEIGH — Proceedings of the 42nd Design Automation Conference

William H. Joyner Jr., Grant Martin, Andrew B. Kahng
Proceedings of the 42nd Design Automation Conference
DAC, 2005.

SYS

@proceedings{DAC-2005,
	acmid         = "1065579",
	address       = "San Diego, California, USA",
	editor        = "William H. Joyner Jr. and Grant Martin and Andrew B. Kahng",
	isbn          = "1-59593-058-2",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 42nd Design Automation Conference}",
	year          = 2005,
}

Contents (191 items)

DAC-2005-VleeschhouwerEFGRHC #delivery: Differentiate and deliver: leveraging your partners (JV, WE, MJF, AJdG, WCR, JH, RC), p. 1.
DAC-2005-MitraKSZ #challenge #design #fault #logic: Logic soft errors in sub-65nm technologies design and CAD challenges (SM, TK, NS, MZ), pp. 2–4.
DAC-2005-Heidergott #design: SEU tolerant device, circuit and processor design (WH), pp. 5–10.
DAC-2005-MarculescuT #architecture #energy #perspective #variability: Variability and energy awareness: a microarchitecture-level perspective (DM, ET), pp. 11–16.
DAC-2005-PetrovTO #embedded #energy #memory management: Energy-effcient physically tagged caches for embedded processors with virtual memory (PP, DT, AO), pp. 17–22.
DAC-2005-MuttrejaRRJ #embedded #energy #estimation #hybrid #simulation: Hybrid simulation for embedded software energy estimation (AM, AR, SR, NKJ), pp. 23–26.
DAC-2005-SchaumontLQV #architecture #design #energy #multi #thread: Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design (PS, BCCL, WQ, IV), pp. 27–30.
DAC-2005-GaoH #multi #reduction: Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages (FG, JPH), pp. 31–36.
DAC-2005-AbdollahiFP #effectiveness: An effective power mode transition technique in MTCMOS circuits (AA, FF, MP), pp. 37–42.
DAC-2005-JayakumarDK #monitoring #self: A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents (NJ, SD, SPK), pp. 43–46.
DAC-2005-YuanQ #reduction: Enhanced leakage reduction Technique by gate replacement (LY, GQ), pp. 47–50.
DAC-2005-DongR #automation #megamodelling #performance: Automated nonlinear Macromodelling of output buffers for high-speed digital applications (ND, JSR), pp. 51–56.
DAC-2005-WeiD #behaviour #development #megamodelling: Systematic development of analog circuit structural macromodels through behavioral model decoupling (YW, AD), pp. 57–62.
DAC-2005-DingV #megamodelling #performance: A combined feasibility and performance macromodel for analog circuits (MD, RV), pp. 63–68.
DAC-2005-BacchiniMDMPSEU #named: ESL: building the bridge between systems to silicon (FB, DM, TD, PM, SAP, SS, SKE, PU), pp. 69–70.
DAC-2005-ChangZNV #analysis #parametricity #statistics: Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions (HC, VZ, SN, CV), pp. 71–76.
DAC-2005-ZhanSLPNS #analysis #statistics: Correlation-aware statistical timing analysis with non-gaussian delay distributions (YZ, AJS, XL, LTP, DN, MS), pp. 77–82.
DAC-2005-ZhangCHGC #analysis #polynomial #statistics: Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model (LZ, WC, YH, JAG, CCPC), pp. 83–88.
DAC-2005-KhandelwalS #analysis #correlation #framework #statistics: A general framework for accurate statistical timing analysis considering correlations (VK, AS), pp. 89–94.
DAC-2005-LiK #architecture: Locality-conscious workload assignment for array-based computations in MPSOC architectures (FL, MTK), pp. 95–100.
DAC-2005-GheorghitaSBC #automation #detection #estimation: Automatic scenario detection for improved WCET estimation (SVG, SS, TB, HC), pp. 101–104.
DAC-2005-KimK #array #design #embedded #memory management #optimisation #scheduling: Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design (JK, TK), pp. 105–110.
DAC-2005-JejurikarG #embedded #realtime #scheduling: Dynamic slack reclamation with procrastination scheduling in real-time embedded systems (RJ, RKG), pp. 111–116.
DAC-2005-VolkerinkM #architecture #using: Response compaction with any number of unknowns using a new LFSR architecture (EHV, SM), pp. 117–122.
DAC-2005-XuNC #constraints #design #embedded #multi #optimisation: Multi-frequency wrapper design and optimization for embedded cores under average power constraints (QX, NN, KC), pp. 123–128.
DAC-2005-Pomeranz #detection: N-detection under transparent-scan (IP), pp. 129–134.
DAC-2005-YangWK #architecture: Secure scan: a design-for-test architecture for crypto chips (BY, KW, RK), pp. 135–140.
DAC-2005-XuGFM: A green function-based parasitic extraction method for inhomogeneous substrate layers (CX, RG, TSF, KM), pp. 141–146.
DAC-2005-HuLWD #analysis #integration #novel #using: Analysis of full-wave conductor system impedance over substrate using novel integration techniques (XH, JHL, JW, LD), pp. 147–152.
DAC-2005-BeattieZDK #3d #distributed #modelling: Spatially distributed 3D circuit models (MWB, HZ, AD, BK), pp. 153–158.
DAC-2005-GopeCJ #3d #multi #named #performance: DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures (DG, IC, VJ), pp. 159–162.
DAC-2005-JiangCC #3d #algorithm #linear #named #order: ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction (RJ, YHC, CCPC), pp. 163–166.
DAC-2005-WassungZABH #design: Choosing flows and methodologies for SoC design (DW, YZ, MSA, MB, CH), p. 167.
DAC-2005-SherwaniMABGLRS #exclamation: DFM rules! (NAS, SLM, AA, PB, CG, HL, PR, AS), pp. 168–169.
DAC-2005-LiQTWCH #approach #clustering #performance: Partitioning-based approach to fast on-chip decap budgeting and minimization (HL, ZQ, SXDT, LW, YC, XH), pp. 170–175.
DAC-2005-LuSHZCHH #navigation #network: Navigating registers in placement for clock network minimization (YL, CCNS, XH, QZ, YC, LH, JH), pp. 176–181.
DAC-2005-NiehHH: Minimizing peak current via opposite-phase clock tree (YTN, SHH, SYH), pp. 182–185.
DAC-2005-SuWKLK #analysis #effectiveness #embedded #functional #performance: A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis (HS, DW, CVK, FL, BK), pp. 186–189.
DAC-2005-ZhaoZD #constraints #robust: Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits (CZ, YZ, SD), pp. 190–195.
DAC-2005-MukherjeeMM #resource management #synthesis: Temperature-aware resource allocation and binding in high-level synthesis (RM, SOM, GM), pp. 196–201.
DAC-2005-TangZB #library #optimisation #power management #synthesis: Leakage power optimization with dual-Vth library in high-level synthesis (XT, HZ, PB), pp. 202–207.
DAC-2005-GuWDZ #behaviour #design #incremental #physics: Incremental exploration of the combined physical and behavioral design space (Z(G, JW, RPD, HZ), pp. 208–213.
DAC-2005-SaneeiAN #encoding #power management #reduction: Sign bit reduction encoding for low power applications (MS, AAK, ZN), pp. 214–217.
DAC-2005-NieKT #incremental #layout: A watermarking system for IP protection by a post layout incremental router (TN, TK, MT), pp. 218–221.
DAC-2005-TiriHHLYSV #embedded #encryption: A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing (KT, DDH, AH, BCL, SY, PS, IV), pp. 222–227.
DAC-2005-TiriV #modelling #simulation: Simulation models for side-channel information leaks (KT, IV), pp. 228–233.
DAC-2005-ChoM #network #pattern matching #security: A pattern matching coprocessor for network security (YHC, WHMS), pp. 234–239.
DAC-2005-Balderas-ContrerasC #encryption #network #performance: High performance encryption cores for 3G networks (TBC, RC), pp. 240–243.
DAC-2005-GuptaRRJ #authentication #embedded #performance: Efficient fingerprint-based user authentication for embedded systems (PG, SR, AR, NKJ), pp. 244–247.
DAC-2005-LiuCO #approximate #design #multi: Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design (YL, SC, WTO), pp. 248–253.
DAC-2005-SauerGS #composition #embedded #framework #implementation #platform: Modular domain-specific implementation and exploration framework for embedded software platforms (CS, MG, SS), pp. 254–259.
DAC-2005-ChenDHSW #analysis #concurrent #design #simulation: Simulation based deadlock analysis for system level designs (XC, AD, HH, ALSV, YW), pp. 260–265.
DAC-2005-ManolacheEP #communication #energy #fault #latency: Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC (SM, PE, ZP), pp. 266–269.
DAC-2005-ZykovMJVS #architecture #novel #performance #trade-off: High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs (AVZ, EM, MFJ, GdV, AS), pp. 270–273.
DAC-2005-MokhoffZRNPK #how: How to determine the necessity for emerging solutions (NM, YZ, KNR, HN, FP, KSK), pp. 274–275.
DAC-2005-ChinneryK #perspective: Closing the power gap between ASIC and custom: an ASIC perspective (DGC, KK), pp. 275–280.
DAC-2005-ChangD #perspective: Explaining the gap between ASIC and custom power: a custom perspective (AC, WJD), pp. 281–284.
DAC-2005-PuriSB: Keeping hot chips cool (RP, LS, SB), pp. 285–288.
DAC-2005-NandraDMDHLSA: Interconnects are moving from MHz→GHz should you be afraid?: or... “my giga hertz, does yours?” (NN, PD, RM, JFD, AH, BL, JS, JA), pp. 289–290.
DAC-2005-ChenardCZP #design: Design methodology for wireless nodes with printed antennas (JSC, CYC, ZZ, MP), pp. 291–296.
DAC-2005-MengBISLK #algorithm #design #estimation #performance: MP core: algorithm and design techniques for efficient channel estimation in wireless applications (YM, APB, RAI, TS, HL, RK), pp. 297–302.
DAC-2005-EberleBPC #communication #design #energy: From myth to methodology: cross-layer design for energy-efficient wireless communication (WE, BB, SP, FC), pp. 303–308.
DAC-2005-ManiDO #algorithm #constraints #performance #statistics: An efficient algorithm for statistical minimization of total power under timing yield constraints (MM, AD, MO), pp. 309–314.
DAC-2005-SinghNLS #geometry #programming #robust: Robust gate sizing by geometric programming (JS, VN, ZQL, SSS), pp. 315–320.
DAC-2005-AgarwalCBZ #analysis #optimisation #statistics #using: Circuit optimization using statistical static timing analysis (AA, KC, DB, VZ), pp. 321–324.
DAC-2005-SuC #algorithm: An exact jumper insertion algorithm for antenna effect avoidance/fixing (BYS, YWC), pp. 325–328.
DAC-2005-KaruriFKLAM #design #fine-grained #profiling #source code: Fine-grained application source code profiling for ASIP design (KK, MAAF, SK, RL, GA, HM), pp. 329–334.
DAC-2005-BanerjeeBD #architecture #clustering #configuration management: Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration (SB, EB, NDD), pp. 335–340.
DAC-2005-KimK05a #evaluation #modelling #performance #pipes and filters #reuse #simulation: Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse (HYK, TGK), pp. 341–344.
DAC-2005-KimYH #using: Trace-driven HW/SW cosimulation using virtual synchronization technique (DK, YY, SH), pp. 345–348.
DAC-2005-NassifZMMPV #exclamation #what: The Titanic: what went wrong! (SRN, PSZ, CM, MM, SDP, WV), pp. 349–350.
DAC-2005-BacchiniRCLLRW #platform: Wireless platforms: GOPS for cents and MilliWatts (FB, JMR, AC, FL, RL, UR, DW), pp. 351–352.
DAC-2005-KheterpalRHMTSP #design: Design methodology for IC manufacturability based on regular logic-bricks (VK, VR, TGH, DM, YT, AJS, LTP), pp. 353–358.
DAC-2005-YangCS #analysis: Advanced timing analysis based on post-OPC extraction of critical dimensions (JY, LC, DS), pp. 359–364.
DAC-2005-GuptaKKS #analysis: Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions (PG, ABK, YK, DS), pp. 365–368.
DAC-2005-MitraYP #named #performance #simulation #using: RADAR: RET-aware detailed routing using fast lithography simulations (JM, PY, DZP), pp. 369–372.
DAC-2005-SasaoM #composition #functional #logic #multi #representation: BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition (TS, MM), pp. 373–378.
DAC-2005-AbdollahiP #canonical #logic #performance #synthesis #verification: A new canonical form for fast boolean matching in logic synthesis and verification (AA, MP), pp. 379–384.
DAC-2005-LiSB #bound #effectiveness #problem: Effective bounding techniques for solving unate and binate covering problems (XYL, MFMS, FB), pp. 385–390.
DAC-2005-WanR #linear #reduction: Operator-based model-order reduction of linear periodically time-varying systems (YW, JSR), pp. 391–396.
DAC-2005-Vasudevan #simulation: Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits (VV), pp. 397–402.
DAC-2005-TiwaryR #megamodelling #on-demand #scalability: Scalable trajectory methods for on-demand analog macromodel extraction (SKT, RAR), pp. 403–408.
DAC-2005-KrenikB #network: Cognitive radio techniques for wide area networks (WK, AB), pp. 409–412.
DAC-2005-GilbertCS #network: MIMO technology for advanced wireless local area networks (JMG, WJC, QS), pp. 413–415.
DAC-2005-Nguyen #architecture: RF MEMS in wireless architectures (CTCN), pp. 416–420.
DAC-2005-MetzgenN #implementation #multi #reduction: Multiplexer restructuring for FPGA implementation cost reduction (PM, DN), pp. 421–426.
DAC-2005-LingSB #case study: FPGA technology mapping: a study of optimality (ACL, DPS, SDB), pp. 427–432.
DAC-2005-SinghMB #incremental #physics #synthesis: Incremental retiming for FPGA physical synthesis (DPS, VM, SDB), pp. 433–438.
DAC-2005-EguroHS #adaptation #architecture: Architecture-adaptive range limit windowing for simulated annealing FPGA placement (KE, SH, AS), pp. 439–444.
DAC-2005-JainKSC #abstraction #refinement #verification #word: Word level predicate abstraction and refinement for verifying RTL verilog (HJ, DK, NS, EMC), pp. 445–450.
DAC-2005-ParthasarathyICB #learning: Structural search for RTL with predicate learning (GP, MKI, KTC, FB), pp. 451–456.
DAC-2005-WedlerSK #normalisation: Normalization at the arithmetic bit level (MW, DS, WK), pp. 457–462.
DAC-2005-MonyBPK #proving: Exploiting suspected redundancy without proving it (HM, JB, VP, RK), pp. 463–466.
DAC-2005-SahooJIDE #concurrent #multi #reachability #thread: Multi-threaded reachability (DS, JJ, SKI, DLD, EAE), pp. 467–470.
DAC-2005-NordinMHP #automation #fourier #generative: Automatic generation of customized discrete fourier transform IPs (GN, PAM, JCH, MP), pp. 471–474.
DAC-2005-HuangNL #scheduling: Race-condition-aware clock skew scheduling (SHH, YTN, FPL), pp. 475–478.
DAC-2005-BhuniaBCMR #approach #novel #power management #reduction #synthesis #using: A novel synthesis approach for active leakage power reduction using dynamic supply gating (SB, NB, QC, HMM, KR), pp. 479–484.
DAC-2005-NepalBMPZ #design #logic #probability: Designing logic circuits for probabilistic computation in the presence of noise (KN, RIB, JLM, WRP, AZ), pp. 485–490.
DAC-2005-McGeeN #classification #design #framework #pipes and filters: A lattice-based framework for the classification and design of asynchronous pipelines (PBM, SMN), pp. 491–496.
DAC-2005-TamH: Power optimal dual-Vdd buffered tree considering buffer stations and blockages (KHT, LH), pp. 497–502.
DAC-2005-GoplenSS: Net weighting to reduce repeater counts during placement (BG, PS, SSS), pp. 503–508.
DAC-2005-SzeAHS: Path based buffer insertion (CCNS, CJA, JH, WS), pp. 509–514.
DAC-2005-RenPAV #migration: Diffusion-based placement migration (HR, DZP, CJA, PV), pp. 515–520.
DAC-2005-BacchiniMFBNMD #question #verification: Is methodology the highway out of verification hell? (FB, GM, HF, JB, MN, SM, LD), pp. 521–522.
DAC-2005-ChangS #analysis #correlation #power management #process: Full-chip analysis of leakage power under process variations, including spatial correlations (HC, SSS), pp. 523–528.
DAC-2005-AziziKDN #design #power management #scalability: Variations-aware low-power design with voltage scaling (NA, MMK, VD, FNN), pp. 529–534.
DAC-2005-SrivastavaSASBD #correlation #estimation #parametricity #performance #power management: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance (AS, SS, KA, DS, DB, SWD), pp. 535–540.
DAC-2005-BhardwajV #random: Leakage minimization of nano-scale circuits in the presence of systematic and random variations (SB, SBKV), pp. 541–546.
DAC-2005-UrardPGMLYG: A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3) (PU, LP, PG, TM, VL, EY, BG), pp. 547–548.
DAC-2005-RoyannezMDWSBBCSDSPRK #design #framework #platform #reduction: A design platform for 90-nm leakage reduction techniques (PR, HM, FD, MW, MS, LB, JB, HC, GS, JD, DS, BP, CR, UK), pp. 549–550.
DAC-2005-NatarajanKH: A 24 GHz phased-array transmitter in 0.18µm CMOS (AN, AK, AH), pp. 551–552.
DAC-2005-SuhKL #architecture: Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs (TS, DK, HHSL), pp. 553–558.
DAC-2005-KimPTVD #adaptation #latency: A low latency router supporting adaptivity for on-chip interconnects (JK, DP, TT, NV, CRD), pp. 559–564.
DAC-2005-PasrichaDBB #architecture #automation #communication #synthesis: Floorplan-aware automated synthesis of bus-based communication architectures (SP, NDD, EB, MBR), pp. 565–570.
DAC-2005-SekarLRD #architecture #communication #configuration management #named: FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology (KS, KL, AR, SD), pp. 571–574.
DAC-2005-HeitheckerE #requirements: Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements (SH, RE), pp. 575–578.
DAC-2005-NookalaCLS #approach #architecture #design #statistics #using: Microarchitecture-aware floorplanning using a statistical design of experiments approach (VN, YC, DJL, SSS), pp. 579–584.
DAC-2005-XiuR: Timing-driven placement by grid-warping (ZX, RAR), pp. 585–591.
DAC-2005-BrennerS #algorithm #performance: Faster and better global placement by a new transportation algorithm (UB, MS), pp. 591–596.
DAC-2005-HoCCC #architecture #multi: Multilevel full-chip routing for the X-based architecture (TYH, CFC, YWC, SJC), pp. 597–602.
DAC-2005-Magee #development #matlab #realtime #testing #verification: Matlab extensions for the development, testing and verification of real-time DSP software (DPM), pp. 603–606.
DAC-2005-BhattM #design #development #matlab: Matlab as a development environment for FPGA design (TMB, DM), pp. 607–610.
DAC-2005-FoxCMHHJKYZ #approach #question: Should our power approach be current? (TF, LC, SM, DH, EPH, VJ, AK, AY, PSZ), p. 611.
DAC-2005-IranliP #named #scalability: DTM: dynamic tone mapping for backlight scaling (AI, MP), pp. 612–617.
DAC-2005-LiC #architecture #embedded: Application/architecture power co-optimization for embedded systems powered by renewable sources (DL, PHC), pp. 618–623.
DAC-2005-YanZJ #interactive #latency #scalability: User-perceived latency driven voltage scaling for interactive applications (LY, LZ, NKJ), pp. 624–627.
DAC-2005-ZhuoC #energy #scheduling: System-level energy-efficient dynamic task scheduling (JZ, CC), pp. 628–631.
DAC-2005-XuHLNBP #design #named #nondeterminism #optimisation #robust: OPERA: optimization with ellipsoidal uncertainty for robust analog IC design (YX, KLH, XL, IN, SPB, LTP), pp. 632–637.
DAC-2005-RenG #framework #optimisation #synthesis: A unified optimization framework for equalization filter synthesis (JR, MRG), pp. 638–643.
DAC-2005-BhattacharyaJS #optimisation: Template-driven parasitic-aware optimization of analog integrated circuit layouts (SB, NJ, CJRS), pp. 644–647.
DAC-2005-NieuwoudtM #approach #multi #optimisation: Multi-level approach for integrated spiral inductor optimization (AN, YM), pp. 648–651.
DAC-2005-AminMKDCHI #analysis #how #question #statistics: Statistical static timing analysis: how simple can we get? (CSA, NM, KK, FD, UC, NH, YII), pp. 652–657.
DAC-2005-CaoC #approach #modelling #performance #process #statistics #towards #variability: Mapping statistical process variations toward circuit performance variability: an analytical modeling approach (YC, LTC), pp. 658–663.
DAC-2005-Li #analysis #grid #performance #power management #simulation: Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation (PL), pp. 664–669.
DAC-2005-WolfsthalG #question #verification: Formal verification: is it real enough? (YW, RMG), pp. 670–671.
DAC-2005-Rossi #design #formal method #question #scalability #verification: Can we really do without the support of formal methods in the verification of large designs? (UR), pp. 672–673.
DAC-2005-Chatterjee #design #process #verification: Streamline verification process with formal property verification to meet highly compressed design cycle (PC), pp. 674–677.
DAC-2005-AhmadM #logic: TCAM enabled on-chip logic minimization (SA, RNM), pp. 678–683.
DAC-2005-NedevschiPB #hardware #low cost #power management #recognition #speech #user interface: Hardware speech recognition for user interfaces in low cost, low power devices (SN, RKP, EAB), pp. 684–689.
DAC-2005-ChenK #embedded #java #reliability #virtual machine: Improving java virtual machine reliability for memory-constrained embedded systems (GC, MTK), pp. 690–695.
DAC-2005-Goldfeder #embedded #multi: Frequency-based code placement for embedded multiprocessors (CG), pp. 696–699.
DAC-2005-CoburnRR #estimation #paradigm: Power emulation: a new paradigm for power estimation (JC, SR, AR), pp. 700–705.
DAC-2005-WeiR #configuration management #implementation #power management #trade-off: Implementing low-power configurable processors: practical options and tradeoffs (JW, CR), pp. 706–711.
DAC-2005-LuoYYB #design #network #power management #using: Low power network processor design using clock gating (YL, JY, JY, LNB), pp. 712–715.
DAC-2005-JayakumarK #approach #design: A variation tolerant subthreshold design approach (NJ, SPK), pp. 716–719.
DAC-2005-LinH #performance #reduction: Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction (YL, LH), pp. 720–725.
DAC-2005-TomL #clustering #design #logic #scalability: Logic block clustering of large designs for channel-width constrained FPGAs (MT, GGL), pp. 726–731.
DAC-2005-BeckC #configuration management: Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility (ACSB, LC), pp. 732–737.
DAC-2005-GanaiGA #model checking #safety #satisfiability: Beyond safety: customized SAT-based model checking (MKG, AG, PA), pp. 738–743.
DAC-2005-BabicBH #performance #satisfiability: Efficient SAT solving: beyond supercubes (DB, JDB, AJH), pp. 744–749.
DAC-2005-JinS #performance: Prime clauses for fast enumeration of satisfying assignments to boolean circuits (HJ, FS), pp. 750–753.
DAC-2005-ZhangPHS #abstraction #satisfiability #using: Dynamic abstraction using SAT-based BMC (LZ, MRP, MSH, TS), pp. 754–757.
DAC-2005-NagarajBSBNLH #variability: BEOL variability and impact on RC extraction (NSN, TB, AS, CB, UN, VL, AMH), pp. 758–759.
DAC-2005-GuardianiBDMM #effectiveness #process: An effective DFM strategy requires accurate process and IP pre-characterization (CG, MB, ND, MM, PM), pp. 760–761.
DAC-2005-TschanzBD: Variation-tolerant circuits: circuit solutions and techniques (JT, KAB, VD), pp. 762–763.
DAC-2005-Najm #analysis #on the #statistics: On the need for statistical timing analysis (FNN), pp. 764–765.
DAC-2005-BlaauwC #tool support: CAD tools for variation tolerance (DB, KC), p. 766.
DAC-2005-NowakR #question: Are there economic benefits in DFM? (MN, RR), pp. 767–768.
DAC-2005-AdirABPS #approach #architecture #testing #verification: A generic micro-architectural test plan approach for microprocessor verification (AA, HA, EB, OP, KS), pp. 769–774.
DAC-2005-HangalCNC #automation #design #hardware #invariant #named: IODINE: a tool to automatically infer dynamic invariants for hardware designs (SH, NC, SN, SC), pp. 775–778.
DAC-2005-AdirADLRVCCD #case study #named #parallel #verification: VLIW: a case study of parallelism verification (AA, YA, BD, YL, MR, MV, MAC, AC, GD), pp. 779–782.
DAC-2005-WagnerBA #approach #automation #generative #monitoring #named #process #testing: StressTest: an automatic approach to test generation via activity monitors (IW, VB, TMA), pp. 783–788.
DAC-2005-EzerJ #configuration management #verification: Smart diagnostics for configurable processor verification (SE, SJ), pp. 789–794.
DAC-2005-CheonHKRW #power management: Power-aware placement (YC, PHH, ABK, SR, QW), pp. 795–800.
DAC-2005-ChowdharyRVCTPH #how #question: How accurately can we model timing in a placement engine? (AC, KR, SV, TC, VT, YP, BH), pp. 801–806.
DAC-2005-TennakoonS #modelling #performance: Efficient and accurate gate sizing with piecewise convex delay models (HT, CS), pp. 807–812.
DAC-2005-PengL #named #performance #power management #using: Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method (YP, XL), pp. 813–818.
DAC-2005-GeilenBS #data flow #graph #model checking #requirements: Minimising buffer requirements of synchronous dataflow graphs with model checking (MG, TB, SS), pp. 819–824.
DAC-2005-SuC05a #synthesis: Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips (FS, KC), pp. 825–830.
DAC-2005-Zhu #analysis #pointer #scalability #towards: Towards scalable flow and context sensitive pointer analysis (JZ), pp. 831–836.
DAC-2005-LeeGML #named #optimisation: MiniBit: bit-width optimization via affine arithmetic (DUL, AAG, OM, WL), pp. 837–840.
DAC-2005-WuZN #approach #estimation #parametricity: A non-parametric approach for dynamic range estimation of nonlinear systems (BW, JZ, FNN), pp. 841–844.
DAC-2005-KajiharaFWMHS #process: Path delay test compaction with process variation tolerance (SK, MF, XW, TM, SH, YS), pp. 845–850.
DAC-2005-TopalogluO #approach #process: A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs (ROT, AO), pp. 851–856.
DAC-2005-DililloGPVB #analysis #comparison #fault #injection: Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies (LD, PG, SP, AV, MB), pp. 857–862.
DAC-2005-MonnetRL #evaluation #fault: Asynchronous circuits transient faults sensitivity evaluation (YM, MR, RL), pp. 863–868.
DAC-2005-MuellerSGS #performance: Deterministic approaches to analog performance space exploration (PSE) (DM, GS, HEG, US), pp. 869–874.
DAC-2005-BernardinisNV #design #platform: Mixed signal design space exploration through analog platforms (FDB, PN, ALSV), pp. 875–880.
DAC-2005-GielenME #modelling #performance #synthesis: Performance space modeling for hierarchical synthesis of analog integrated circuits (GGEG, TM, TE), pp. 881–886.
DAC-2005-WilsonGHMLBTC #framework #platform #question: Structured/platform ASIC apprentices: which platform will survive your board room? (RW, JG, CH, KM, SL, IB, RT, RC), pp. 887–888.
DAC-2005-CortesEP #energy #realtime: Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints (LAC, PE, ZP), pp. 889–894.
DAC-2005-ChoiCK #embedded #power management: DC-DC converter-aware power management for battery-operated embedded systems (YC, NC, TK), pp. 895–900.
DAC-2005-RaoV #energy #set: Energy optimal speed control of devices with discrete speed sets (RR, SBKV), pp. 901–904.
DAC-2005-ZhangLLSS #realtime #scheduling: Optimal procrastinating voltage scheduling for hard real-time systems (YZ, ZL, JL, KS, MRS), pp. 905–908.
DAC-2005-WongKP #flexibility #multi: Flexible ASIC: shared masking for multiple media processors (JLW, FK, MP), pp. 909–914.
DAC-2005-ChengWLLH #architecture #reduction: Device and architecture co-optimization for FPGA power reduction (LC, PW, FL, YL, LH), pp. 915–920.
DAC-2005-GayasenVI: Exploring technology alternatives for nano-scale FPGA interconnects (AG, NV, MJI), pp. 921–926.
DAC-2005-AminID #approximate #using: Piece-wise approximations of RLCK circuit responses using moment matching (CSA, YII, FD), pp. 927–932.
DAC-2005-SouMD #approach #optimisation #order #reduction: A quasi-convex optimization approach to parameterized model order reduction (KCS, AM, LD), pp. 933–938.
DAC-2005-ZhouMA #reduction: Structure preserving reduction of frequency-dependent interconnect (QZ, KM, ACA), pp. 939–942.
DAC-2005-KlemasDW #algorithm #order #reduction: Segregation by primary phase factors: a full-wave algorithm for model order reduction (TJK, LD, JKW), pp. 943–946.

William H. Joyner Jr., Grant Martin, Andrew B. KahngProceedings of the 42nd Design Automation ConferenceDAC, 2005.

Contents (191 items)

William H. Joyner Jr., Grant Martin, Andrew B. Kahng
Proceedings of the 42nd Design Automation Conference
DAC, 2005.