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Travelled to:
1 × USA
Collaborated with:
S.Sinha Q.Su J.Kawa C.Chiang
Talks about:
manufactur (1) variat (1) consid (1) yield (1) model (1) intra (1) die (1)

Person: Jianfeng Luo

DBLP DBLP: Luo:Jianfeng

Contributed to:

DAC 20062006

Wrote 1 papers:

DAC-2006-LuoSSKC
An IC manufacturing yield model considering intra-die variations (JL, SS, QS, JK, CC), pp. 749–754.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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