BibSLEIGH — Proceedings of the 43rd Design Automation Conference

Ellen Sentovich
Proceedings of the 43rd Design Automation Conference
DAC, 2006.

SYS

@proceedings{DAC-2006,
	acmid         = "1146909",
	address       = "San Francisco, California, USA",
	editor        = "Ellen Sentovich",
	isbn          = "1-59593-381-6",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 43rd Design Automation Conference}",
	year          = 2006,
}

Contents (219 items)

DAC-2006-HartungKHPJY #how #question: How will the fabless model survive? (TH, JK, AH, BP, FJ, NY), pp. 1–2.
DAC-2006-Josephson #debugging: The good, the bad, and the ugly of silicon debug (DJ), pp. 3–6.
DAC-2006-AbramoviciBDLMM #configuration management #framework: A reconfigurable design-for-debug infrastructure for SoCs (MA, PB, KND, PL, GM, DM), pp. 7–12.
DAC-2006-HsuTJC #debugging: Visibility enhancement for silicon debug (YCH, FST, WJ, YTC), pp. 13–18.
DAC-2006-ZouMGS #optimisation: A CPPLL hierarchical optimization methodology considering jitter, power and locking time (JZ, DM, HEG, US), pp. 19–24.
DAC-2006-EeckelaertSGSS #design #optimisation #standard: Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard (TE, RS, GGEG, MS, WMCS), pp. 25–30.
DAC-2006-TiwaryTR #design #generative: Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration (SKT, PKT, RAR), pp. 31–36.
DAC-2006-TanimotoYNH #realtime #using: A real time budgeting method for module-level-pipelined bus based system using bus scenarios (TT, SY, AN, TH), pp. 37–42.
DAC-2006-JayaseelanLM: Exploiting forwarding to improve data bandwidth of instruction-set extensions (RJ, HL, TM), pp. 43–48.
DAC-2006-IsseninBDD #analysis #memory management #multi #reuse: Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies (II, EB, BD, ND), pp. 49–52.
DAC-2006-ZhuQ #fault tolerance #multi #prototype #runtime: Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery (XZ, WQ), pp. 53–56.
DAC-2006-AgarwalN #analysis #statistics: Statistical analysis of SRAM cell stability (KA, SRN), pp. 57–62.
DAC-2006-XiongZVV #statistics: Criticality computation in parameterized statistical timing (JX, VZ, NV, CV), pp. 63–68.
DAC-2006-KanjJN #analysis #design: Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events (RK, RVJ, SRN), pp. 69–72.
DAC-2006-YangCTRC #design: An up-stream design auto-fix flow for manufacturability enhancement (JY, EC, CT, NR, MC), pp. 73–76.
DAC-2006-SingerMBHK #question #what: The IC nanometer race — what will it take to win? (GS, PM, DB, FCH, HKK), pp. 77–78.
DAC-2006-BrierM #architecture #c #c++ #modelling #using #verification: Use of C/C++ models for architecture exploration and verification of DSPs (DB, RSM), pp. 79–84.
DAC-2006-BruceHNBRL #consistency #design #maintenance: Maintaining consistency between systemC and RTL system designs (ACB, MMKH, AN, SB, NR, CKL), pp. 85–89.
DAC-2006-Swan #modelling #transaction #verification: SystemC transaction level models and RTL verification (SS), pp. 90–92.
DAC-2006-GeorgelinK #design #equivalence #towards: Towards a C++-based design methodology facilitating sequential equivalence checking (PG, VK), pp. 93–96.
DAC-2006-PakbazniaFP #analysis #concept: Charge recycling in MTCMOS circuits: concept and analysis (EP, FF, MP), pp. 97–102.
DAC-2006-LiLP #analysis #power management #statistics: Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions (XL, JL, LTP), pp. 103–108.
DAC-2006-KimSKE #design #physics #power management #standard: Physical design methodology of power gating circuits for standard-cell-based design (HOK, YS, HK, IE), pp. 109–112.
DAC-2006-ShiH #challenge #design #implementation #power management: Challenges in sleep transistor design and implementation in low-power designs (KS, DH), pp. 113–116.
DAC-2006-ChengDCW #algorithm #generative #performance #power management #reduction: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction (LC, LD, DC, MDFW), pp. 117–120.
DAC-2006-ChiouCCY #power management: Timing driven power gating (DSC, SHC, SCC, CY), pp. 121–124.
DAC-2006-KhatibPBBBKJN #analysis #architecture #design #monitoring #multi #realtime: A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration (IAK, FP, DB, LB, MB, HK, AJ, RN), pp. 125–130.
DAC-2006-JonesHDTSFCM #automation #configuration management #power management: An automated, reconfigurable, low-power RFID tag (AKJ, RRH, SRD, SCT, RS, JF, JTC, MHM), pp. 131–136.
DAC-2006-LeeOMC #design #multi #prototype: Design space exploration and prototyping for on-chip multimedia applications (HGL, ÜYO, RM, NC), pp. 137–142.
DAC-2006-ChangSC #design #evaluation #trade-off: Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs (KCC, JSS, TFC), pp. 143–148.
DAC-2006-LeeWA #analysis #statistics: Refined statistical static timing analysis through (BNL, LCW, MSA), pp. 149–154.
DAC-2006-SinghS #analysis #component #correlation #independence #parametricity #statistics #using: Statistical timing analysis with correlated non-gaussian parameters using independent component analysis (JS, SSS), pp. 155–160.
DAC-2006-WangKO #nondeterminism #parametricity #probability #statistics: Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty (WSW, VK, MO), pp. 161–166.
DAC-2006-SingheeFMR #probability #statistics #tool support #towards: Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools (AS, CFF, JDM, RAR), pp. 167–172.
DAC-2006-WilsonZ: Decision-making for complex SoCs in consumer electronic products (RW, YZ), p. 173.
DAC-2006-YangCBDSK #question: Entering the hot zone: can you handle the heat and be cool? (AY, RC, SB, JAD, SS, UK), pp. 174–175.
DAC-2006-McPherson #challenge #reliability: Reliability challenges for 45nm and beyond (JWM), pp. 176–181.
DAC-2006-LiuMM #analysis #design #reliability #tool support: Design tools for reliability analysis (ZL, BM, JZM), pp. 182–187.
DAC-2006-BandiDK #communication #design #reliability: Design in reliability for communication designs (URB, MD, PKK), pp. 188–192.
DAC-2006-PomplSHNS #analysis #aspect-oriented #design #reliability: Practical aspects of reliability analysis for IC designs (TP, CS, MH, HN, JS), pp. 193–198.
DAC-2006-PantC #grid #physics #power management: Power grid physics and implications for CAD (SP, EC), pp. 199–204.
DAC-2006-YuSH #analysis #grid #order #performance #power management #reduction: Fast analysis of structured power grid by triangularization based structure preserving model order reduction (HY, YS, LH), pp. 205–210.
DAC-2006-GhantaVBP #analysis #correlation #power management #probability #scalability: Stochastic variational analysis of large power grids considering intra-die correlations (PG, SBKV, SB, RP), pp. 211–216.
DAC-2006-ZhaoPSYF #algorithm #linear #megamodelling #performance #programming #using: A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming (MZ, RP, SS, SY, YF), pp. 217–222.
DAC-2006-NevoF #distributed #order: Distributed dynamic BDD reordering (ZN, MF), pp. 223–228.
DAC-2006-ZhuKKS #satisfiability: SAT sweeping with local observability don’t-cares (QZ, NK, AK, ALSV), pp. 229–234.
DAC-2006-WangGG #deduction #difference #learning #logic: Predicate learning and selective theory deduction for a difference logic solver (CW, AG, MKG), pp. 235–240.
DAC-2006-VimjamH #identification #induction #performance #satisfiability: Fast illegal state identification for improving SAT-based induction (VCV, MSH), pp. 241–246.
DAC-2006-AminKMKC #library #multi: A multi-port current source model for multiple-input switching effects in CMOS library cells (CSA, CVK, NM, KK, EC), pp. 247–252.
DAC-2006-FatemiNP #analysis #logic #statistics #using: Statistical logic cell delay analysis using a current-based model (HF, SN, MP), pp. 253–256.
DAC-2006-WongB #multi #performance #polynomial: Multi-shift quadratic alternating direction implicit iteration for high-speed positive-real balanced truncation (NW, VB), pp. 257–260.
DAC-2006-WongC #matrix #performance: A fast passivity test for descriptor systems via structure-preserving transformations of Skew-Hamiltonian/Hamiltonian matrix pencils (NW, CKC), pp. 261–266.
DAC-2006-LiS #linear #network #order #reduction: Model order reduction of linear networks with massive ports via frequency-dependent port packing (PL, WS), pp. 267–272.
DAC-2006-MokhoffZ #trade-off: Tradeoffs and choices for emerging SoCs in high-end applications (NM, YZ), p. 273.
DAC-2006-Martin #challenge #design #overview: Overview of the MPSoC design challenge (GM), pp. 274–279.
DAC-2006-JerrayaBP #abstraction #interface #modelling #multi #programming: Programming models and HW-SW interfaces abstraction for multi-processor SoC (AAJ, AB, FP), pp. 280–285.
DAC-2006-FlakeDS #design #tool support: System-level exploration tools for MPSoC designs (PF, SJD, FS), pp. 286–287.
DAC-2006-LiuCLLW #design #mobile #video: Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications (TML, CCC, CYL, TAL, SZW), pp. 288–289.
DAC-2006-PanCHCLCLLHWLLTYMCCPHCH #ram: A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications (JSP, HCC, BYH, HCC, RL, CHC, YCL, CL, LH, CLW, MHL, CYL, SNT, JNY, CPM, YC, SHC, HCP, PCH, BC, AH), pp. 290–291.
DAC-2006-HattoriIIYKSYNYKTHAHTSMYHMYHTYIKMYITAAO #mobile #power management: Hierarchical power distribution and power management scheme for a single chip mobile processor (TH, TI, MI, EY, HK, GS, TY, KN, HY, TK, YT, MH, HA, IH, KT, YS, NM, YY, TH, YM, KY, KH, ST, SY, TI, YK, HM, TY, NI, RT, NA, TA, KO), pp. 292–295.
DAC-2006-WaghmodeLS #scalability: Buffer insertion in large circuits with constructive solution search techniques (MW, ZL, WS), pp. 296–301.
DAC-2006-PengL #constraints #power management: Low-power repeater insertion with both delay and slew rate constraints (YP, XL), pp. 302–307.
DAC-2006-HuAHKLSS #algorithm #performance: Fast algorithms for slew constrained minimum cost buffering (SH, CJA, JH, SKK, ZL, WS, CCNS), pp. 308–313.
DAC-2006-IyengarGT #flexibility #scalability: A flexible and scalable methodology for GHz-speed structural test (VI, GG, MT), pp. 314–319.
DAC-2006-AhmedTJ #fault: Timing-based delay test for screening small delay defects (NA, MT, VJ), pp. 320–325.
DAC-2006-MajumdarCG #analysis #validation: Hold time validation on silicon and the relevance of hazards in timing analysis (AM, WYC, JG), pp. 326–331.
DAC-2006-Gluska #verification: Practical methods in coverage-oriented verification of the merom microprocessor (AG), pp. 332–337.
DAC-2006-ShimizuGKOAMS #verification: Verification of the cell broadband engineTM processor (KS, SG, TK, TO, JA, LM, TS), pp. 338–343.
DAC-2006-WagnerBA #design #logic: Shielding against design flaws with field repairable control logic (IW, VB, TMA), pp. 344–347.
DAC-2006-NahirZEKR #generative #multi #testing #verification: Scheduling-based test-case generation for verification of multimedia SoCs (AN, AZ, RE, TK, NR), pp. 348–351.
DAC-2006-ZhouP #agile #embedded #low cost #realtime: Rapid and low-cost context-switch through embedded processor customization for real-time and control applications (XZ, PP), pp. 352–357.
DAC-2006-SuhendraMRC #analysis #detection #performance: Efficient detection and exploitation of infeasible paths for software timing analysis (VS, TM, AR, TC), pp. 358–363.
DAC-2006-HuangG #embedded #scalability: Leakage-aware intraprogram voltage scaling for embedded processors (PKH, SG), pp. 364–369.
DAC-2006-HosseiniPCUGB #design #question #standard #verification: Building a standard ESL design and verification methodology: is it just a dream? (AH, AP, HTC, PU, EFG, SB), pp. 370–371.
DAC-2006-Kahng #challenge #design #multi: CAD challenges for leading-edge multimedia designs (ABK), p. 372.
DAC-2006-ChoP #named: BoxRouter: a new global router based on box expansion and progressive ILP (MC, DZP), pp. 373–378.
DAC-2006-HuLHL #network: Steiner network construction for timing critical nets (SH, QL, JH, PL), pp. 379–384.
DAC-2006-ShiMYH #simulation: Circuit simulation based obstacle-aware Steiner routing (YS, PM, HY, LH), pp. 385–388.
DAC-2006-AlpertKSW: Timing-driven Steiner trees are (practically) free (CJA, ABK, CCNS, QW), pp. 389–392.
DAC-2006-PsarakisGHPRR #pipes and filters #self: Systematic software-based self-test for pipelined processors (MP, DG, MH, AMP, AR, SR), pp. 393–398.
DAC-2006-ChenRPR #algorithm: A test pattern ordering algorithm for diagnosis with truncated fail data (GC, SMR, IP, JR), pp. 399–404.
DAC-2006-Al-Yamani: DFT for controlled-impedance I/O buffers (AAAY), pp. 405–410.
DAC-2006-NassifPRSBR #analysis #question: Variation-aware analysis: savior of the nanometer era? (SRN, VP, NR, DS, CB, RR), pp. 411–412.
DAC-2006-AnanthanR #physics #process: A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS (HA, KR), pp. 413–418.
DAC-2006-JayakumarGGK #approach #design: A PLA based asynchronous micropipelining approach for subthreshold circuit design (NJ, RG, BG, SPK), pp. 419–424.
DAC-2006-KeaneEKSK #framework #logic: Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing (JK, HE, TTHK, SSS, CHK), pp. 425–428.
DAC-2006-WuWL: Timing-constrained and voltage-island-aware voltage assignment (HW, MDFW, IML), pp. 429–432.
DAC-2006-CongZ #algorithm #performance #scheduling: An efficient and versatile scheduling algorithm based on SDC formulation (JC, ZZ), pp. 433–438.
DAC-2006-HuangCNY: Register binding for clock period minimization (SHH, CHC, YTN, WCY), pp. 439–444.
DAC-2006-VermaI #architecture #automation #towards: Towards the automatic exploration of arithmetic-circuit architectures (AKV, PI), pp. 445–450.
DAC-2006-WangGDK #design #optimisation #using: Design space exploration using time and resource duality with the ant colony optimization (GW, WG, BD, RK), pp. 451–454.
DAC-2006-GuptaGP #agile #estimation #specification: Rapid estimation of control delay from high-level specifications (GRG, MG, PRP), pp. 455–458.
DAC-2006-CohnKMTT #challenge #design #game studies #multi #platform: Design challenges for next-generation multimedia, game and entertainment platforms (JMC, JTK, CM, RT, BT), p. 459.
DAC-2006-GopalakrishnanLP #architecture #metric #using: Architecture-aware FPGA placement using metric embedding (PG, XL, LTP), pp. 460–465.
DAC-2006-SafarpourVBY #performance #satisfiability: Efficient SAT-based Boolean matching for FPGA technology mapping (SS, AGV, GB, RY), pp. 466–471.
DAC-2006-LinCC #clustering #optimisation: Optimal simultaneous mapping and clustering for FPGA delay optimization (JYL, DC, JC), pp. 472–477.
DAC-2006-HuLHT #reduction: Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction (YH, YL, LH, TT), pp. 478–483.
DAC-2006-InoueIKSE #architecture #mobile #named: VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals (HI, AI, MK, JS, ME), pp. 484–489.
DAC-2006-WangLLYHWH #design #framework #network #platform #security: A network security processor design based on an integrated SOC design and test platform (CHW, CYL, MSL, JCY, CTH, CWW, SYH), pp. 490–495.
DAC-2006-AroraRRSJC #architecture #mobile #multi #security: Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC (DA, AR, SR, MS, NKJ, STC), pp. 496–501.
DAC-2006-RagelP #monitoring #named #reliability #security: IMPRES: integrated monitoring for processor reliability and security (RGR, SP), pp. 502–505.
DAC-2006-ElbazTSGBM #encryption: A parallelized way to provide data encryption and integrity checking on a processor-memory bus (RE, LT, GS, PG, MB, AM), pp. 506–509.
DAC-2006-ZhangMBC #detection #representation #satisfiability #scalability #simulation #symmetry #using: Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability (JSZ, AM, RKB, MCJ), pp. 510–515.
DAC-2006-Wang #detection #symmetry: Exploiting K-Distance Signature for Boolean Matching and G-Symmetry Detection (KHW), pp. 516–521.
DAC-2006-SinghMPO #nondeterminism #runtime: Gain-based technology mapping for minimum runtime leakage under input vector uncertainty (AKS, MM, RP, MO), pp. 522–527.
DAC-2006-SwahnH: Gate sizing: finFETs vs 32nm bulk MOSFETs (BS, SH), pp. 528–531.
DAC-2006-MishchenkoCB #fresh look #logic #synthesis: DAG-aware AIG rewriting a fresh look at combinational logic synthesis (AM, SC, RKB), pp. 532–535.
DAC-2006-DebaillieBLVC #design #energy: Energy-scalable OFDM transmitter design and control (BD, BB, GL, GV, FC), pp. 536–541.
DAC-2006-MukherjeeM: Systematic temperature sensor allocation and placement for microprocessors (RM, SOM), pp. 542–547.
DAC-2006-KumarSPJ #approach #coordination #named: HybDTM: a coordinated hardware-software approach for dynamic thermal management (AK, LS, LSP, NKJ), pp. 548–553.
DAC-2006-WuJYLT #estimation #functional: A systematic method for functional unit power estimation in microprocessors (WW, LJ, JY, PL, SXDT), pp. 554–557.
DAC-2006-BurginCHMMSKFF #adaptation #algorithm #architecture #implementation #power management #trade-off: Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm (FB, FC, MH, HM, RMP, RS, HK, NF, WF), pp. 558–561.
DAC-2006-ZhuoCCV #hybrid: Extending the lifetime of fuel cell based hybrid systems (JZ, CC, NC, SBKV), pp. 562–567.
DAC-2006-ChoCCV #cost analysis #embedded #energy #power management: High-level power management of embedded systems with application-specific energy cost functions (YC, NC, CC, SBKV), pp. 568–573.
DAC-2006-HuZCGC #communication #latency #power management #synthesis: Communication latency aware low power NoC synthesis (YH, YZ, HC, RLG, CKC), pp. 574–579.
DAC-2006-ChenCFX #multi: Optimality study of resource binding with multi-Vdds (DC, JC, YF, JX), pp. 580–585.
DAC-2006-ZhongWS #design #energy #mobile #multi #named: SMERT: energy-efficient design of a multimedia messaging system for mobile devices (LZ, BW, MJS), pp. 586–591.
DAC-2006-MochockiLCH #3d #estimation #mobile: Signature-based workload estimation for mobile 3D graphics (BM, KL, SC, XSH), pp. 592–597.
DAC-2006-GuCO #game studies: Games are up for DVFS (YG, SC, WTO), pp. 598–603.
DAC-2006-IranliLP #mobile #power management: Backlight dimming in power-aware mobile displays (AI, WL, MP), pp. 604–607.
DAC-2006-ChengC: Minimization for LED-backlit TFT-LCDs (WCC, CFC), pp. 608–611.
DAC-2006-MengSK #embedded #power management #reduction: Leakage power reduction of embedded memories on FPGAs through location assignment (YM, TS, RK), pp. 612–617.
DAC-2006-AtienzaVPPBMM #framework #multi #performance: A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip (DA, PGDV, GP, FP, LB, GDM, JMM), pp. 618–623.
DAC-2006-NabaaAN #adaptation #architecture #process: An adaptive FPGA architecture with process variation compensation and reduced leakage (GN, NA, FNN), pp. 624–629.
DAC-2006-SrinivasanMXVS #named: FLAW: FPGA lifetime awareness (SS, PM, YX, NV, KS), pp. 630–635.
DAC-2006-MacNeilS: Solution-processed infrared photovoltaic devices (DDM, EHS), pp. 636–638.
DAC-2006-AmirtharajahWCSZ #energy: Circuits for energy harvesting sensor signal processing (RA, JW, JC, JS, BZ), pp. 639–644.
DAC-2006-Paradiso #mobile: Systems for human-powered mobile computing (JAP), pp. 645–650.
DAC-2006-KansalHSR #network #power management: Harvesting aware power management for sensor networks (AK, JH, MBS, VR), pp. 651–656.
DAC-2006-CortadellaKG #architecture #synthesis: Synthesis of synchronous elastic architectures (JC, MK, BG), pp. 657–662.
DAC-2006-PandeyG #communication #constraints #scalability #statistics #synthesis: Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint (SP, MG), pp. 663–668.
DAC-2006-AksoyCFM #constraints #integer #linear #optimisation #programming #satisfiability #synthesis #using: Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming (LA, EACdC, PFF, JM), pp. 669–674.
DAC-2006-CongFHJZ #behaviour #communication: Behavior and communication co-optimization for systems with sequential communication media (JC, YF, GH, WJ, ZZ), pp. 675–678.
DAC-2006-SovianiHE #pipes and filters #synthesis: Synthesis of high-performance packet processing pipelines (CS, IH, SAE), pp. 679–682.
DAC-2006-HanGCJ #memory management #optimisation #video: Buffer memory optimization for video codec application modeled in Simulink (SIH, XG, SIC, AAJ), pp. 689–694.
DAC-2006-VianaGKBV #configuration management #performance: Configurable cache subsetting for fast cache tuning (PV, AGR, EJK, EB, FV), pp. 695–700.
DAC-2006-YangLD #memory management #operating system: High-performance operating system controlled memory compression (LY, HL, RPD), pp. 701–704.
DAC-2006-StojanovicBDW #effectiveness #implementation #queue: A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors (VS, RIB, JD, RW), pp. 705–708.
DAC-2006-BorkarBCNSS #question: Tomorrow’s analog: just dead or just different? (SYB, RWB, JHC, EN, DS, CS), pp. 709–710.
DAC-2006-ZhangJS #architecture #configuration management #hybrid #named: NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture (WZ, NKJ, LS), pp. 711–716.
DAC-2006-PaulFOL #analysis #modelling #performance: Modeling and analysis of circuit performance of ballistic CNFET (BCP, SF, MO, TL), pp. 717–722.
DAC-2006-RaoOK #architecture #logic: Topology aware mapping of logic functions onto nanowire-based crossbar architectures (WR, AO, RK), pp. 723–726.
DAC-2006-RadT #clustering #hybrid: A new hybrid FPGA with nanoscale clusters and CMOS routing (RMR, MT), pp. 727–730.
DAC-2006-GoraiBBTM #protocol #verification: Directed-simulation assisted formal verification of serial protocol and bridge (SG, SB, LB, PT, RSM), pp. 731–736.
DAC-2006-NanshiS #simulation: Guiding simulation with increasingly refined abstract traces (KN, FS), pp. 737–742.
DAC-2006-WuH #bound #constraints #equivalence #mining: Mining global constraints for improving bounded sequential equivalence checking (WW, MSH), pp. 743–748.
DAC-2006-LuoSSKC: An IC manufacturing yield model considering intra-die variations (JL, SS, QS, JK, CC), pp. 749–754.
DAC-2006-ChenCCCH #novel: Novel full-chip gridless routing considering double-via insertion (HYC, MFC, YWC, LC, BH), pp. 755–760.
DAC-2006-WangZ #bound: Optimal jumper insertion for antenna avoidance under ratio upper-bound (JW, HZ), pp. 761–766.
DAC-2006-Miskov-ZivanovM #fault #modelling #named #reduction: MARS-C: modeling and reduction of soft errors in combinational circuits (NMZ, DM), pp. 767–772.
DAC-2006-GargJKC #approach #design: A design approach for radiation-hard digital electronics (RG, NJ, SPK, GC), pp. 773–778.
DAC-2006-AziziN #product line: A family of cells to reduce the soft-error-rate in ternary-CAM (NA, FNN), pp. 779–784.
DAC-2006-YuSP #modelling #process: Process variation aware OPC with variational lithography modeling (PY, SXS, DZP), pp. 785–790.
DAC-2006-BhardwajVGC #analysis #modelling #optimisation #process: Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits (SB, SBKV, PG, YC), pp. 791–796.
DAC-2006-HuebbersDI #parametricity #performance #process: Computation of accurate interconnect process parameter values for performance corners under process variations (FH, AD, YII), pp. 797–800.
DAC-2006-CaoDH #standard: Standard cell characterization considering lithography induced variations (KC, SD, JH), pp. 801–804.
DAC-2006-BergeronFPMAS #testing #verification: Building a verification test plan: trading brute force for finesse (JB, HF, AP, RSM, CA, DS), pp. 805–806.
DAC-2006-Borkar: Electronics beyond nano-scale CMOS (SB), pp. 807–808.
DAC-2006-BanerjeeS #future of #question: Are carbon nanotubes the future of VLSI interconnections? (KB, NS), pp. 809–814.
DAC-2006-Prinz: The zen of nonvolatile memories (EJP), pp. 815–820.
DAC-2006-PillSCRBC #analysis #formal method #hardware #requirements: Formal analysis of hardware requirements (IP, SS, RC, MR, RB, AC), pp. 821–826.
DAC-2006-BanerjeePDKD #game studies #generative #specification #testing: Test generation games from formal specifications (AB, BP, SD, AK, PD), pp. 827–832.
DAC-2006-LeungT #performance #scheduling: Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems (LFL, CYT), pp. 833–838.
DAC-2006-OgrasM #predict: Prediction-based flow control for network-on-chip traffic (ÜYO, RM), pp. 839–844.
DAC-2006-MuraliABM #delivery #fault tolerance #multi #network: A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip (SM, DA, LB, GDM), pp. 845–848.
DAC-2006-LiZJ #concurrent #named #network #proximity: DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip (ML, QAZ, WBJ), pp. 849–852.
DAC-2006-ShethSM #design: The importance of adopting a package-aware chip design flow (KS, ES, JM), pp. 853–856.
DAC-2006-Patel: Silicon carrier for computer systems (CSP), pp. 857–862.
DAC-2006-OzturkCK #approach #constraints #network #optimisation #parallel: Optimizing code parallelization through a constraint network based approach (ÖÖ, GC, MTK), pp. 863–688.
DAC-2006-SheahanFWMM #challenge #design: 4.25 Gb/s laser driver: design challenges and EDA tool limitations (BS, JWF, JW, KM, BM), pp. 863–866.
DAC-2006-HatamkhaniLSY #design #performance: Power-centric design of high-speed I/Os (HH, FL, VS, CKKY), pp. 867–872.
DAC-2006-NuzzoPBPGT: A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW (PN, GVdP, FDB, LVdP, BG, PT), pp. 873–878.
DAC-2006-NieuwoudtRM #named #optimisation #synthesis: SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers (AN, TR, YM), pp. 879–884.
DAC-2006-HammoudaSDTNBAS #design #framework #migration: Chameleon ART: a non-optimization based analog design migration framework (SH, HS, MD, MT, QN, WMB, HMA, HIS), pp. 885–888.
DAC-2006-GoffioulVDDC #consistency #design #object-oriented #using: Ensuring consistency during front-end design using an object-oriented interfacing tool called NETLISP (MG, GV, JVD, BD, BC), pp. 889–892.
DAC-2006-HsuRKPB #data flow #graph #performance #simulation: Efficient simulation of critical synchronous dataflow graphs (CJH, SR, MYK, JLP, SSB), pp. 893–898.
DAC-2006-StuijkGB #constraints #data flow #graph #requirements #throughput #trade-off: Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs (SS, MG, TB), pp. 899–904.
DAC-2006-KlingaufGBPB #modelling #named #transaction: GreenBus: a generic interconnect fabric for transaction level modelling (WK, RG, OB, PP, MB), pp. 905–910.
DAC-2006-HerreraV #embedded #framework #modelling #specification: A framework for embedded system specification under different models of computation in SystemC (FH, EV), pp. 911–914.
DAC-2006-RiccobeneSRB #design #embedded #modelling: A model-driven design environment for embedded systems (ER, PS, AR, SB), pp. 915–918.
DAC-2006-PistolLD #automation #design #self: Design automation for DNA self-assembled nanostructures (CP, ARL, CD), pp. 919–924.
DAC-2006-HwangSC #array #automation #design: Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications* (WLH, FS, KC), pp. 925–930.
DAC-2006-YuhYC #using: Placement of digital microfluidic biochips using the t-tree formulation (PHY, CLY, YWC), pp. 931–934.
DAC-2006-BudnikRBR: A high density, carbon nanotube capacitor for decoupling applications (MMB, AR, AB, KR), pp. 935–938.
DAC-2006-CarmonaC #encoding #scalability: State encoding of large asynchronous controllers (JC, JC), pp. 939–944.
DAC-2006-LinZ #algorithm #constraints #performance: An efficient retiming algorithm under setup and hold constraints (CL, HZ), pp. 945–950.
DAC-2006-WangDC #approach #named #scheduling #tool support: ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling (KW, LD, XC), pp. 951–954.
DAC-2006-NakamuraTOTY #design #scalability: Budgeting-free hierarchical design method for large scale and high-performance LSIs (YN, MT, TO, ST, KY), pp. 955–958.
DAC-2006-DavoodiS #optimisation #variability: Variability driven gate sizing for binning yield optimization (AD, AS), pp. 959–964.
DAC-2006-ZhouM #energy #estimation: Elmore model for energy estimation in RC trees (QZ, KM), pp. 965–970.
DAC-2006-GhoshMKR #power management #reduction #self: Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM (SG, SM, KK, KR), pp. 971–976.
DAC-2006-DadgourJB #architecture #novel #power management: A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates (HFD, RVJ, KB), pp. 977–982.
DAC-2006-ShahGK #library #optimisation #reduction #standard: Standard cell library optimization for leakage reduction (SS, PG, ABK), pp. 983–986.
DAC-2006-BrahmbhattZWQ #adaptation #algorithm #encoding #hybrid #power management #using: Low-power bus encoding using an adaptive hybrid algorithm (ARB, JZ, QW, QQ), pp. 987–990.
DAC-2006-LoiASLSB #3d #analysis #performance: A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy (GLL, BA, NS, SCL, TS, KB), pp. 991–996.
DAC-2006-HuaMSSMJD #3d: Exploring compromises among timing, power and temperature in three-dimensional integrated circuits (HH, CM, KS, AMS, SM, RJ, WRD), pp. 997–1002.
DAC-2006-ShiC #array #performance: Efficient escape routing for hexagonal array of high density I/Os (RS, CKC), pp. 1003–1008.
DAC-2006-MandrekarBSES #analysis: System level signal and power integrity analysis methodology for system-in-package applications (RM, KB, KS, EE, MS), pp. 1009–1012.
DAC-2006-BerezaTWKP #named: PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations (WB, YT, SW, TAK, RHP), pp. 1013–1016.
DAC-2006-LaiR #megamodelling #multi #performance #robust: A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators (XL, JSR), pp. 1017–1022.
DAC-2006-WeiD #composition #development #megamodelling: Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling (YW, AD), pp. 1023–1028.
DAC-2006-MeiR #robust: A robust envelope following method applicable to both non-autonomous and oscillatory circuits (TM, JSR), pp. 1029–1034.
DAC-2006-YuL #modelling #simulation #statistics: Lookup table based simulation and statistical modeling of Sigma-Delta ADCs (GY, PL), pp. 1035–1040.
DAC-2006-GuthausSB #programming #using: Clock buffer and wire sizing using sequential programming (MRG, DS, RBB), pp. 1041–1046.
DAC-2006-VattikondaWC #design #modelling #robust: Modeling and minimization of PMOS NBTI effect for robust nanometer design (RV, WW, YC), pp. 1047–1052.
DAC-2006-YangCGJ #algorithm #matrix #parallel #rank #scalability: A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures (CY, SC, DG, VJ), pp. 1053–1056.
DAC-2006-KarlBSM #modelling #reliability: Reliability modeling and management in dynamic microprocessor-based systems (EK, DB, DS, TNM), pp. 1057–1060.
DAC-2006-RawatCKSGZS #named #proving #question: DFM: where’s the proof of value? (SR, RC, AK, JS, MG, NZ, AS), pp. 1061–1062.
DAC-2006-FengH #equivalence #verification: Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification (XF, AJH), pp. 1063–1068.
DAC-2006-DupenloupLM #abstraction #functional #verification: Transistor abstraction for the functional verification of FPGAs (GD, TL, RM), pp. 1069–1072.
DAC-2006-AwedhS #automation #bound #invariant #model checking: Automatic invariant strengthening to prove properties in bounded model checking (MA, FS), pp. 1073–1076.
DAC-2006-PeranandamNRWKR #bound #performance: Fast falsification based on symbolic bounded property checking (PMP, PKN, JR, RJW, TK, WR), pp. 1077–1082.
DAC-2006-ChaoCWCW #analysis #using: Unknown-tolerance analysis and test-quality control for test response compaction using space compactors (MCTC, KTC, SW, STC, WW), pp. 1083–1088.
DAC-2006-MrugalskiRT #programmable: Test response compactor with programmable selector (GM, JR, JT), pp. 1089–1094.
DAC-2006-VrankenGGSH #detection #fault: Fault detection and diagnosis with parity trees for space compaction of test responses (HPEV, SKG, AG, JS, FH), pp. 1095–1098.
DAC-2006-NelsonBDB #detection #multi #physics: Multiple-detect ATPG based on physical neighborhoods (JEN, JGB, RD, RD(B), pp. 1099–1102.
DAC-2006-MoffittNMP #constraints: Constraint-driven floorplan repair (MDM, ANN, ILM, MEP), pp. 1103–1108.
DAC-2006-ShamYC: Optimal cell flipping in placement and floorplanning (CWS, EFYY, CCNC), pp. 1109–1114.
DAC-2006-LuoNP #design #incremental #performance: A new LP based incremental timing driven placement for high performance designs (TL, DN, DZP), pp. 1115–1120.

Ellen SentovichProceedings of the 43rd Design Automation ConferenceDAC, 2006.

Contents (219 items)

Ellen Sentovich
Proceedings of the 43rd Design Automation Conference
DAC, 2006.