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Travelled to:
1 × France
Collaborated with:
S.Kundu
Talks about:
placement (1) silicon (1) process (1) variat (1) impact (1) buffer (1) studi (1) mitig (1) clock (1) tune (1)

Person: Kelageri Nagaraj

DBLP DBLP: Nagaraj:Kelageri

Contributed to:

DATE 20092009

Wrote 1 papers:

DATE-2009-NagarajK #case study #process
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation (KN, SK), pp. 292–295.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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